Method and apparatus for improving latchup immunity in a dual-polysilicon gate process
AssigneeMicron Technology, Inc.
InventorMonte Manning
Life of this patent
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Abstract
The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.
Claims55
A method for increasing latch-up immunity in a semiconductor circuit, comprising the following steps:
- a) creating a well region having a first type conductivity in a substrate having a second type conductivity;
- b) creating a first active device having said second type conductivity in said well region;
- c) creating a second active device having said first type conductivity in said substrate outside of said well region;
- and
- d) creating a trench in said substrate between said first active device and said second active device thereby increasing a distance minority carriers must travel between said first and said second active devices, thereby increasing the latch-up immunity.
A method of forminig a portion of an integrated circuit, comprising:
- forming a first region having a first conductivity in a substrate;
- forming a second region having a second conductivity in the first region having the first conductivity;
- forming a first active device in the first region having the first conductivity;
- forming a second active device in the second region having the second conductivity;
- and
- forming a trench disposed from the surface of the substrate in the substrate at a position between the first and second active devices, wherein the trench is electrically isolated from regions having a common conductivity selected from the group consisting of regions having the first conductivity and regions having the second conductivity.
A method of forming a portion of an integrated circuit, comprising:
- forming a first doped region of a substrate, wherein the first doped region has a first conductivity;
- forming a second doped region of the substrate, wherein the second doped region has a second conductivity;
- forming a first active device in the first doped region;
- forming a second active device in the second doped region;
- and
- forming a trench disposed from the surface of the substrate in the first doped region at a position between the first and second active devices, wherein the trench is electrically isolated from doped regions having the second conductivity.
A method of forming a portion of an integrated circuit, comprising:
- forming a first doped region of a substrate, wherein the first doped region has a first conductivity;
- forming a second doped region of the substrate, wherein the second doped region has a second conductivity opposite the first conductivity, still further wherein the second doped region forms a well within the first doped region;
- forming a first active device in the first doped region, wherein the first active device is a metal oxide semiconductor device having the second conductivity;
- forming a second active device in the second doped region, wherein the second active device is a metal oxide semiconductor device having the first conductivity;
- forming a trench disposed from the surface of the substrate in the first doped region at a position between the first and second active devices, wherein the trench is electrically isolated from doped regions having the second conductivity;
- and
- forming a third doped region at the base of the trench, wherein the third doped region has the first conductivity, further wherein the third doped region is more highly doped than the first doped region.
Dependencies are inferred from the claim text.