Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line

A method of forming split gate electrode MOSFET devices including the steps comprising:

• form a tunnel oxide layer over a semiconductor substrate,
• form a floating gate electrode layer composed of polysilicon over said tunnel oxide layer,
• form a masking cap comprising a hard mask composed of polysilicon oxide over said floating gate electrode layer,
• pattern a floating gate electrode stack formed by said tunnel oxide layer and said floating gate electrode layer in said pattern of said masking cap using said masking cap as a hard mask,
• form intermetal dielectric and control gate layers over said substrate covering said said masking cap and said stack and locations for future source regions and locations for future drain regions,
• pattern said intermetal dielectric and control gate layers into forming a control gate set covering said masking cap, and said stack, with a portion of said set remaining on said semiconductor substrate beyond the floating gate electrode stack to prepare for the formation of mirror image split gate electrodes,
• etch a source line slot bisecting and extending through said set, said masking cap, and said stack to form a mirror image split gate electrode pair and stacks pairs,
• form a source region by ion implanting through said source line slot through said gate electrode stack including said floating gate electrode and said tunnel oxide layer, and
• form a drain region self-aligned with said split gate electrodes.