US 6,207,501 B1Granted

Method of fabricating a flash memory

AssigneeUnited Microelectronics Corp.

InventorsShou-Wei Hsieh, Shiou-Han Liaw

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Abstract

A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N+ ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N+ ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N− ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area. A process of P− ion implantation is performed to form the PLDD structure, and then the third photo resist is stripped. The second sidewall is formed, and then the fourth photo resist is formed. A process of P+ ion implantation is performed to form the source/drain structure at the PMOS area. Finally, the fourth photo resist is stripped.

Claims36

Dependent claims

A method of fabricating a flash memory, said method comprising the steps of:

(a) providing a P-type semiconductor substrate with an N well and a layer of field oxide, wherein said P-type semiconductor substrate is divided into an NMOS area, a PMOS area in said N well, and a flash memory area;
(b) forming a first layer of polysilicon and a first dielectric layer at said flash memory area;
(c) forming a second layer of polysilicon, a layer of tungsten silicide, and a layer of TEOS on said semiconductor substrate in sequence;
(d) forming a first layer of photo resist to protect said NMOS area and said PMOS area, and then forming a gate structure of a flash cell array at said flash memory area;
(e) performing a first process of ion implantation to form a source/drain structure of said flash cell array;
(f) stripping said first layer of photo resist;
(g) forming a second layer of photo resist to protect said PMOS area, and then forming a gate structure at said NMOS area;
(h) stripping said second layer of photo resist;
(i) performing a second process of ion implantation to form a lightly doped drain (LDD) structure at said NMOS area;
(j) forming a first sidewall;
(k) performing a third process of ion implantation to form a source/drain structure at said NMOS area;
(l) forming a third layer of photo resist to protect said NMOS area and said flash memory area, and then forming a gate structure at said PMOS area;
(m) performing a fourth process of ion implantation to form a lightly doped drain (LDD) structure at said PMOS area;
(n) stripping said third layer of photo resist;
(o) forming a second sidewall;
(p) forming a fourth layer of photo resist to protect said NMOS area and said flash memory area, and performing a fifth process of ion implantation to form a source/drain structure at said PMOS area;
and
(q) stripping said fourth layer of photo resist.

15 more elements

A method of fabricating a flash memory, said method comprising the steps of:

(a) providing a P-type semiconductor substrate with an N well and a layer of field oxide, wherein said P-type semiconductor substrate is divided into an NMOS area, a PMOS area in said N well, and a flash memory area;
(b) forming a first layer of polysilicon and a first dielectric layer at said flash memory area;
(c) forming a second layer of polysilicon, a layer of tungsten silicide, and a layer of TEOS on said semiconductor substrate in sequence;
(d) forming a first layer of photo resist to protect said NMOS area and said PMOS area, and then forming a gate structure of a flash cell array at said flash memory area;
(e) performing a first process of ion implantation to form a source/drain structure of said flash cell array;
(f) stripping said first layer of photo resist;
(g) forming a second layer of photo resist to protect said PMOS area, and then forming a gate structure at said NMOS area;
(h) stripping said second layer of photo resist;
(i) performing a second process of ion implantation to form a lightly doped drain (LDD) structure at said NMOS area;
(j) forming a first sidewall;
(k) performing a third process of ion implantation to form a source/drain structure at said NMOS area;
(l) forming a third layer of photo resist to protect said NMOS area and said flash memory area, and then forming a gate structure at said PMOS area;
(m) performing a fourth process of ion implantation to form a lightly doped drain (LDD) structure at said PMOS area;
(n) forming a second sidewall;
(o) performing a fifth process of ion implantation to form a source/drain structure at said PMOS area;
and
(p) stripping said third layer of photo resist.

14 more elements

A method of fabricating a flash memory, said method comprising the steps of:

(a) providing a P-type semiconductor substrate with an N well and a layer of field oxide, wherein said P-type semiconductor substrate is divided into an NMOS area, a PMOS area in said N well, and a flash memory area;
(b) forming a first layer of polysilicon and a first dielectric layer at said flash memory area;
(c) forming a second layer of polysilicon, a layer of tungsten silicide, and a layer of TEOS on said semiconductor substrate in sequence;
(d) forming a first layer of photo resist to protect said NMOS area and said PMOS area, and then forming a gate structure of a flash cell array at said flash memory area;
(e) performing a first process of ion implantation to form a source/drain structure of said flash cell array;
(f) stripping said first layer of photo resist;
(g) forming a second layer of photo resist to protect said PMOS area, and then forming a gate structure at said NMOS area;
(h) stripping said second layer of photo resist;
(i) performing a second process of ion implantation to form a lightly doped drain (LDD) structure at said NMOS area;
(j) forming a first sidewall;
(k) performing a third process of ion implantation to form a source/drain structure at said NMOS area;
(l) forming a layer of nitride to cover said semiconductor substrate;
(m)forming a third layer of photo resist to protect said NMOS area and said flash memory area, and then forming a gate structure at said PMOS area;
(n) stripping said third layer of photo resist;
(o) performing a fourth process of ion implantation by using said layer of nitride as a hard mask to form a lightly doped drain (LDD) structure at said PMOS area;
(p) forming a second sidewall;
and
(q) performing a fifth process of ion implantation to form a source/drain structure at said PMOS area.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/363,879Filed 29 Jul 1999
Priority: TW 8712078515 Dec 1998
Granted: 27 Mar 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10D 84/0177
Manufacturing their gate conductors: the gate conductors having different materials or different implants
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe