Method of fabricating a coronary-type capacitor in an integrated circuit

A method for fabricating a coronary-type capacitor, the method comprising the steps of:

• preparing a semiconductor substrate, which is formed with at least one MOS transistor having a gate and a pair of source/drain regions;
• forming an insulating layer over the MOS transistor with a contact window in the insulating layer to expose a selected one of the source/drain regions,
• successively forming a first polysilicon layer, a first HSG polysilcon layer, a second polysilicon layer, a second HSG polysilcon layer, a third polysilicon layer, a third HSG polysilcon layer, a fourth polysilicon layer, and a fourth HSG polysilcon layer over the insulating layer, in which the first polysilicon layer is electrically connected to the selected one of the source/drain regions;
• forming a void portion in a stacked structure, which includes the second polysilicon layer, the second HSG polysilcon layer, the third polysilcon layer, the third HSG polysilcon layer, the fourth polysilicon layer, and the fourth HSG polysilcon layers by removing a selected portion of the stacked structure that is substantially located above the selected one of the source/drain regions until the first HSG polysilcon layer is exposed;
• removing selected portions of all the polysilicon layers and all the HSG polysilcon layers other than those portions that are defined as a bottom electrode structure of the capacitor around the void portion;
• and
• performing a selective etching process using an etchant that can react with the polysilicon at a faster etching rate than with the HSG polysilcon so as to cause sidewalls of the polysilicon layers to be more recessed than the sidewalls of the HSG polysilcon layers, wherein the remaining portions of the polysilicon layers and the HSG polysilcon layers in combination constitute a coronary-shaped electrode structure that serves as the bottom electrode of the capacitor.

A method for fabricating a coronary-type capacitor in a semiconductor wafer, the method comprising the steps of:

• preparing a semiconductor substrate, which is formed with at least one MOS transistor having a gate and a pair of source/drain regions;
• forming an insulating layer over the MOS transistor, with a contact window exposing a first one of the source/drain regions,
• successively forming a first doped polysilicon layer, a first HSG polysilcon layer, a second doped polysilicon layer, a second HSG polysilcon layer, a third doped polysilicon layer, a third HSG polysilcon layer, a fourth doped polysilicon layer, and a fourth HSG polysilcon layer over the insulating layer, in which the first doped polysilicon layer is electrically connected to the first one of the source/drain regions;
• performing a heat-treatment process on the wafer so as to activate the impurity ions in all of the doped polysilicon layers;
• forming a void portion in a stacked structure, which includes the second doped polysilicon layer, the second HSG polysilcon layer, the third doped polysilicon layer, the third HSG polysilcon layer, the fourth doped polysilicon layer, and the fourth HSG polysilcon layer, by removing a selected portion of the stacked structure that is substantially located above the first one of the source/drain regions until the first HSG polysilcon layer is exposed;
• removing selected portions of all the doped polysilicon layers and all the HSG polysilcon layers other than those portions that are defined as a bottom electrode structure of the capacitor around the void portion;
• and
• performing a selective etching process using an etchant that can react with polysilicon at a faster etching rate than with HSG polysilcon so as to cause sidewalls of the doped polysilicon layers to be more recessed than the sidewalls of the HSG polysilcon layers, wherein the remaining portions of the doped polysilicon layers and the HSG polysilcon layers in combination constitute a coronary-shaped electrode structure that serves as the bottom electrode of the capacitor.