Buffering tree analysis in mapped design
AssigneeLSI Logic Corporation
InventorGuy Dupenloup
Life of this patent
Estimating the term…
Abstract
A method of determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design comprising the steps of determining source pins of the nets of the buffering tree, determining fanout of each of said source pins, determining active edges and active levels of each of said source pins, and presenting said source pins, said fanout, and said active edge on a report.
Claims19
A method of determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design, said method comprising the steps of:
- determining a root pin of the buffering tree;
- determining leaf pins of the buffering tree;
- determining fanout of said root pin;
- determining active edges and active levels of each of said leaf pins;
- and
- presenting said root pin, said fanout, said leafs and said active edges and active levels on a report.
An apparatus for determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design, comprising:
- a processor;
- memory connected to said processor;
- said memory having instructions for said processor to
- determine the root pin of the buffering tree;
- determine the leaf pins of the buffering tree;
- determine the fanout of the root pin;
- determine active edges and active levels of each of said leaf pins;
- and
- present said root pin, said fanout, said leafs and said active edges and active levels on a report.
An apparatus for determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design, comprising:
- means for determining the root pin of the buffering tree;
- means for determining the leaf pins of the buffering tree;
- means for determining the fanout of the root pin;
- means for determining active edges and active levels of each of said leaf pins;
- and
- presenting said root pin, said fanout, said leafs and said active edges and active levels on a report.
A computer storage medium containing instructions for determining circuit characteristics of buffering tree nets of an integrated circuit (IC) design, said instructions comprising the steps of:
- determining the root pin of the buffering tree;
- determining the leaf pins of the buffering tree;
- determining the fanout of the root pin;
- determining active edges and active levels of each of said leaf pins;
- and
- presenting said root pin, said fanout, said leafs and said active edges and active levels on a report.
Dependencies are inferred from the claim text.