Method for designing LSI circuit pattern

A method for designing an LSI circuit pattern which includes a configuration in which a driver gate and a plurality of load gates are connected by a wiring branched in the middle thereof, wherein,

• a portion of the wiring extending from the driver gate to a load gate of interest included in the plurality of load gates is set to be a wiring of interest, while a portion of the wiring extending from a wiring branch point on the wiring of interest to a load gate of no interest included in the plurality of load gates is set to be a branch wiring, and an actual gate delay time is calculated by correcting a gate delay time obtained in the case where there is no wiring load and by using a formula below:
• Tpd=tpd+Rtr×(Cd+Cw)+Rw×k1×Cf+Rw×k2×Cd+Rw×k3×Cw,
• wherein
• tpd:
• the gate delay time obtained in the case where there is no wiring load;
• Rtr:
• an ON resistance of a transistor included in the driver gate;
• Cf:
• a total value of fan-out capacitances of transistors included in the respective load gates;
• Cd:
• a wiring capacitance of the branch wiring;
• Cw:
• a wiring capacitance of the wiring of interest;
• Rw:
• a wiring resistance of the wiring of interest;
• and
• k1, k2 and k3:
• a constant which takes on a value ranging from 0 to 1 inclusive.

A method for designing an LSI circuit pattern for pattern-designing a plurality of gates and a wiring pattern which connects the plurality of gates on an LSI chip, the method comprising the steps of:

• increasing a driver size of a driver gate included in the plurality of gates in the case where the gate delay time, calculated upon designing the plurality of gates in the wiring patterns on the LSI chip, exceeds the prescribed target value;
• inserting a repeater between the driver gate and the load gate included in the plurality of gates in the case where a gate delay time recalculated after the step of increasing a driver size exceeds the prescribed target value;
• and
• widening a metal pitch of the wiring pattern in the case where a gate delay time recalculated after the step of inserting a repeater exceeds the prescribed target value.