Fault simulation method and apparatus, and storage medium storing fault simulation program

A fault simulation apparatus for detecting a fault in an integrated circuit, which is adapted to assume one of a plurality of circuit states, using a plurality of test patterns, said apparatus comprising:

• a circuit dividing section for logically dividing said integrated circuit, which is an object of fault simulation into a forward circuit area, which is a combinational circuit area on an input-pin side of a storage element included in said integrated circuit, and a backward circuit area, which is a combinational circuit except said forward circuit area;
• a test pattern generation section for generating test pattern sets one at a time;
• a pattern accumulation section for accumulating the series test pattern sets generated by said test pattern generation section;
• a pattern arrangement section for arranging said series test pattern sets, which are stored in said pattern accumulation section, in parallel;
• a parallel pattern true-value simulation section to perform true-value simulation in a true state, where there is not any fault, by inputting said parallel test pattern, which is a group of a plurality of test patterns, into said integrated circuit;
• a parallel pattern fault simulation section to perform forward fault simulation for detecting a fault in said forward circuit area by inputting and propagating a fault into said forward circuit area after stabilization of the true-value simulation, and to check whether the fault is propagated through said integrated circuit on the basis of a difference between a result of the true value simulation and a result of the fault simulation;
• and
• a fault passage section for, if a fault which is propagated to the input pins of said storage element during the course of simulation by the parallel pattern fault simulation section is in said forward circuit area, to write the value of the fault into the storage element at the observation time of the fault, and at a later observation time, to read the value of the fault from said storage element and to propagate the value of the fault to a combinational circuit area connected to output pins of said storage element.

A storage medium to store a fault simulation program for automatically detecting a fault in an integrated circuit by a computer and through use of a test pattern, and to cause the computer to operate as:

• circuit dividing means for logically dividing the integrated circuit, which is an object of fault simulation, into a forward circuit area, which is a combinational circuit area on an input-pin side of a storage element included in said integrated circuit, and a backward circuit area, which is a combinational circuit except said forward area;
• test pattern generation means for generating test pattern sets one at a time;
• pattern arrangement means for arranging said series test pattern sets generated by said test pattern generation means in parallel;
• parallel pattern true-value simulation means for performing true-value simulation in a true state, where there is not any fault, by inputting said parallel test pattern, which is a group of a plurality of test patterns, into the integrated circuit;
• parallel pattern fault simulation means for performing forward fault simulation for detecting fault in said forward circuit area by inputting and propagating a fault into said forward circuit area after stabilization of said true-value simulation, and for checking whether the fault is propagated through said integrated circuit on the basis of a difference between a result of said true-value simulation and a result of said fault simulation;
• and
• fault passage means for, when a fault which is propagated to the input pins of the storage element during the course of simulation for said forward circuit area apart from said backward circuit area, by said parallel pattern fault simulation means, is in said forward circuit area, writing the value of the fault at the observation time of the fault into the storage element, and at later observation time, reading the value of the fault from the storage element and propagating the value of the fault to a combinational circuit connected to output pins of the storage element.

A fault simulation method for detecting a fault in an integrated circuit, which is adapted to assume one of a plurality of circuit states, using a plurality of test patterns, said method comprising the steps of:

• logically dividing an integrated circuit, which is an object of fault simulation, into a forward circuit area, which is a combinational circuit area on an input-pin side of a storage element included in said integrated circuit, and a backward circuit area, which is a combinational circuit except said forward circuit area;
• performing backward fault simulation for detecting a fault in said backward circuit area of the integrated circuit in a first circuit state using one of the test patterns;
• performing forward fault simulation for a forward circuit area of said integrated circuit;
• and
• writing a value of the fault at that observation time into said storage element, and at a later observation time, reading said value of the fault from the storage element and propagating the value of the fault to a combinational circuit connected to output pins of said storage element, if a fault which propagates to input pins of said storage element exists in said forward circuit area during said forward fault simulation.

A fault simulation apparatus for detecting a fault in an integrated circuit, comprising:

• a circuit dividing section for logically dividing the integrated circuit, which is an object of fault simulation, into a forward circuit area, which is a combinational circuit area on an input-pin side of a storage element included in said integrated circuit, and a backward circuit area, which is a combinational circuit except said forward circuit area;
• a parallel pattern fault simulation section to perform fault simulation for detecting a fault in said forward circuit area using parallel test pattern, which is a group of a plurality of test patterns;
• and
• a write monitoring section to detect a propagated fault resulting from transient pulse output of said integrated circuit by storing the propagated fault with a corresponding clock signal in said storage element.