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US 6,205,564 B1Granted
Optimized built-in self-test method and apparatus for random access memories
AssigneeLucent Technologies Inc.
InventorsIlyoung Kim, Yervant Zorian
Life of this patent
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Abstract
A method and apparatus are described for detecting an optimized set of predetermined faults in a memory device which ensure an acceptable quality level. The method and apparatus comprise a BIST March algorithm optimized to accelerate the testing time by reducing the number of read/write operations necessary to detect a set of predetermined faults.
Claims37
A method for detecting faults in a memory array having a plurality of addresses, comprising the steps of:
- (I) executing a first sequence of operations, comprising
- (1) a write operation of a first bit pattern to a memory location at a first of said plurality of addresses,
- (II) executing a second sequence of operations, comprising
- (2) a read operation of said first bit pattern from said memory location at said first address,
- (3) a write operation of a second bit pattern to said memory location at said first address, said second bit pattern being the complement of said first bit pattern,
- (4) a read operation of said second bit pattern from said memory location at said first address,
- (5) a write operation of said first bit pattern to said memory location at said first address,
- (III) executing a third sequence of operations after said second sequence, without the intervention of another operation, comprising
- (6) a read operation of said first bit pattern from said memory location at said first address,
- (7) a write operation of said second bit pattern to said memory location at said first address,
- (IV) executing a fourth sequence of operations after said third sequence, without the intervention of another operation, comprising
- (8) a read operation of said, second bit pattern from said memory location at said first address,
- (9) a write operation of said first bit pattern to said memory location at said first address,
- (10) a read operation of said first bit pattern from said memory location at said first address,
- (11) a write operation of said second bit pattern to said memory location at said first address,
- (V) executing a fifth sequence of operations, comprising
- (12) a read operation of said second bit pattern from said memory location at said first address, and
- (VI) executing a sixth sequence of operations, comprising
- (13) a read operation of said second bit pattern from said memory location at said first address, and
- (14) a write operation of said first bit pattern to said memory location at said first address.
17 more elements
An method for detecting a plurality of faults comprising one of any of a stuck-open fault, a retention fault or a state coupling fault in a memory array having a plurality of addresses, comprising the steps of:
- (I) executing a first sequence of operations, comprising,
- (1) a write operation of a first bit pattern to a memory location at a first of said plurality of addresses,
- (II) executing a second sequence of operations, comprising
- (2) a read operation of said first bit pattern from said memory location at said first address,
- (3) a write operation of a second bit pattern to said memory location at said first address, said second bit pattern being the complement of said first bit pattern,
- (4) a read operation of said second bit pattern from said memory location at said first address,
- (5) a write operation of said first bit pattern to said memory location at said first address,
- (III) executing a third sequence of operations, comprising
- (6) a read operation of said first bit pattern from said memory location at said first address,
- (7) a write operation of said second bit pattern to said memory location at said first address,
- (IV) executing a fourth sequence of operations, comprising
- (8) a read operation of said second bit pattern from said memory location at said first address,
- (9) a write operation of said first bit pattern to said memory location at said first address,
- (10) a read operation of said first bit pattern from said memory location at said first address,
- (11) a write operation of said second bit pattern to said memory location at said first address,
- (V) executing a fifth sequence of operations, comprising
- (12) a read operation of said second bit pattern from said memory location at said first address,
- (VI) executing a sixth sequence of operations, comprising
- (13) a read operation of said second bit pattern from said memory location at said first address,
- (14) a write operation of said first bit pattern to said memory location at said first address, and
- whereby said plurality of faults are detected.
18 more elements
An apparatus for a detecting faults in a memory array having a plurality of addresses, comprising:
- (I) means for executing a first sequence of operations, comprising,
- (1) a write operation of a first bit pattern to a memory location at a first of said plurality of addresses,
- (II) means for executing a second sequence of operations, comprising
- (2) a read operation of said first bit pattern from said memory location at said first address,
- (3) a write operation of a second bit pattern to said memory location at said first address, said second bit pattern being the complement of said first bit pattern,
- (4) a read operation of said second bit pattern from said memory location at said first address,
- (5) a write operation of said first bit pattern to said memory location at said first address,
- (III) means for executing a third sequence of operations after said second sequence, without the intervention of another operation, comprising
- (6) a read operation of said first bit pattern from said memory location at said first address,
- (7) a write operation of said second bit pattern to said memory location at said first address,
- (IV) means for executing a fourth sequence of operations after said third sequence, without the intervention of another operation, comprising
- (8) a read operation of said second bit pattern from said memory location at said first address,
- (9) a write operation of said first bit pattern to said memory location a said first address,
- (10) a read operation of said first bit pattern from said memory location at said first address,
- (11) a write operation of said second bit pattern to said memory location at said first address,
- (V) means for executing a fifth sequence of operations, comprising
- (12) a read operation of said second bit pattern from said memory location at said first address, and
- (VI) means for executing a sixth sequence of operations, comprising
- (13) a read operation of said second bit pattern from said memory location at said first address, and
- (14) a write operation of said first bit pattern to said memory location at said first address.
17 more elements
An apparatus for a detecting faults in a memory device comprising a memory array having a plurality of addresses, comprising:
- a BIST controller coupled to said memory device,
- a CPU coupled to said BIST controller, said CPU enabling execution by said BIST controller of a March algorithm to detect faults comprising one of a stuck-open fault, a retention fault or a state coupling fault in said memory array,
- a test address generator and a test data generator, each coupled to said memory device,
- upon receiving an enabling signal from said CPU, said BIST controller further generating a control signal for said test address generator to generate test vectors to be written into said memory array in a predetermined sequence, said BIST further generating a control signal for said test data generator to provide address vectors and read/write operations to said memory device, and
- said BIST controller further executing said March algorithm according to
- (Wx);
- (Rx,Wy,Ry,Wx);
- (Rx,Wy);
- (Ry,Wx,Rx,Wy);
- (Ry);
- (Ry,Wx)
- wherein indicates a first sequence of memory addresses where the order is immaterial, indicates a second sequence of memory addresses from a first of said plurality of addresses to a last of said plurality of addresses, indicates a third sequence of memory addresses, said third sequence being the complement of said second sequence of memory addresses, Wx indicates a write operation of a first bit pattern x, Wy indicates a write operation of a second bit pattern y, said second bit pattern y being the complement of said first bit pattern x, Rx indicates a read operation of said first bit pattern x and Ry indicates a read operation of said second bit pattern y.
9 more elements
An apparatus for a detecting faults in a memory device comprising a memory array having a plurality of addresses, comprising:
- a BIST controller coupled to said memory device,
- a CPU coupled to said BIST controller, said CPU enabling execution by said BIST controller of a March algorithm to detect faults comprising one of a stuck-open fault, a retention fault or a state coupling fault in said memory array,
- a test address generator and a test data generator, each coupled to said memory device,
- upon receiving an enabling signal from said CPU, said BIST controller further generating a control signal for said test address generator to generate test vectors to be written into said memory array in a predetermined sequence, said BIST further generating a control signal for said test data generator to provide address vectors and read/write operations to said memory device, and
- said BIST controller further executing said March algorithm according to
- (Wx);
- (Rx,Wy,Ry,Wx);
- (Rx,Wy);
- (Ry,Wx,Rx,Wy);
- (Ry);
- (Ry,Wx);
- wherein indicates a first sequence of memory addresses where the order is immaterial, indicates a second sequence of memory addresses from a first of said plurality of addresses to a last of said plurality of addresses, indicates a third sequence of memory addresses, said third sequence being the complement of said second sequence of memory addresses, Wx indicates a write operation of a first bit pattern x, Wy indicates a write operation of a second bit pattern y, said second bit pattern y being the complement of said first bit pattern x, Rx indicates a read operation of said first bit pattern x and Ry indicates a read operation of said second bit pattern y.
9 more elements
A method for a detecting faults in a memory array having a plurality of addresses, comprising the steps of:
- (I) executing a first sequence of operations, comprising
- (1) a write operation of one of a plurality of bit patterns to a memory location at a first of said plurality of addresses,
- (II) executing a second sequence of operations, comprising
- (2) a read operation of said one of said plurality of bit patterns from said memory location at said first address,
- (3) a write operation of a second bit pattern to said memory location at said first address, said second bit pattern being the complement of said one of said plurality of bit patterns,
- (4) a read operation of said second bit pattern from said memory location at said first address,
- (5) a write operation of said one of said plurality of bit patterns to said memory location to said first address,
- (III) executing a third sequence of operations after said second sequence, without the intervention of another operation, comprising
- (6) a read operation of said one of said plurality of bit patterns from said memory location at said first address,
- (7) a write operation of said second bit pattern to said memory location at said first address,
- (IV) executing a fourth sequence of operations after said second sequence, without the intervention of another operation, comprising
- (8) a read operation of said second bit pattern from said memory location at said first address,
- (9) a write operation of said one of said plurality of bit patterns to said memory location at said first address,
- (10) a read operation of said one of said plurality of bit patterns from said memory location at said first address,
- (11) a write operation of said second bit pattern to said memory location at said first address,
- (V) executing a fifth sequence of operations, comprising
- (12) a read operation of said second bit pattern from said memory location at said first address, and
- (VI) executing a sixth sequence of operations, comprising
- (13) a read operation of said second bit pattern from said memory location at said first address, and
- (14) a write operation of said one of said plurality of bit patterns to said memory location at said first address.
17 more elements
Dependencies are inferred from the claim text.