Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG

A method of diagnosing and debugging a processor for executing a stream of instructions, comprising:

• specifying an instruction or data address breakpoint in a set of debug registers;
• specifying one of a plurality of debug mechnaisms in a set of debug configuration registers;
• comparing instructions from the stream of instructions to the breakpoint in the set of debug registers and outputting a match signal in response to a match of an instruction with the breakpoint;
• generating a debug exception in response to the match signal;
• and
• transferring program control to the one of a plurality of debug mechnaisms specified in the set of debug configuration registers.

A computer system for executing a stream of instructions comprising:

• system memory for storing the stream of instructions;
• a system bus connected to said system memory;
• a system bus controller for controlling transfer of the stream of instructions on said system bus;
• a processor connected to said system bus for receiving and executing the stream of instructions stored in said system memory, comprising:
• register means for specifying one of a plurality of debug mechnaisms for transfer of program control;
• and
• means for generating a debug exception;
• and
• wherein the processor transfers program control to the specified debug mechnaisms in response to the debug exception.