Method and apparatus for diagnosing failure occurrence position

A method of diagnosing a test circuit device, comprising the steps of:

• simulating an operation of a test circuit device using a set of test vectors to produce a simulation result:
• testing said test circuit device using said set of test vectors to produce a test result;
• defining a first set of combinations of circuit elements based on a circuit data of said test circuit device, said test circuit device being composed of said circuit elements;
• estimating a final set of failure candidates from said first set of combinations in a failure diagnosing process based on said simulation result and said test result for each of said test vectors;
• and
• outputting said final set of failure candidates,
• wherein said estimating step further includes:
• (o) determining a third set of combinations of said circuit elements in which any failure does not occur, based on said simulation result for a specific test vector, when it is determined that the power source queiscent current fault is present;
• and
• (p) calculating a product of said first set and said second set to redefine the calculating result as said first set when it is determined that the power source queiscent current fault is present.

A failure diagnosing apparatus for a semiconductor integrated circuit device, comprising:

• a circuit data storage unit for storing a circuit data of a semiconductor integrated circuit device;
• a test vector storage unit for storing test vectors for said semiconductor integrated circuit device;
• a simulating unit for simulating an operation of said semiconductor integrated circuit device using said test vectors to produce a simulation result;
• a testing unit for testing said semiconductor integrated circuit device using said test vectors to produce a test result;
• a diagnosing unit for defining a first set of combinations of circuit elements based on said circuit data of said semiconductor integrated circuit device, said semiconductor integrated circuit device being composed of said circuit elements, for estimating a final set of failure candidates from said first set of combinations in a failure diagnosing process while reducing a number of combinations of said first set based on said simulation result and said test result for each of said test vectors;
• an output unit for outputting said final set of failure candidates;
• and
• a layout data storage unit for storing a layout data of said semiconductor integrated circuit device,
• wherein said diagnosing unit defines said first set of combinations of every two of said circuit elements based on said circuit data of said semiconductor integrated circuit device, selects combinations of said circuit elements based on said layout data of said semiconductor integrated circuit device such that any failure does not occur, to define a second set of said selected combinations, and removes said second set from said first set to redefine said first set of combinations.

A failure diagnosing apparatus for a semiconductor integrated circuit device, comprising:

• a circuit data storage unit for storing a circuit data of a semiconductor integrated circuit device;
• a test vector storage unit for storing test vectors for said semiconductor integrated circuit device;
• a simulating unit for simulating an operation of said semiconductor integrated circuit device using said test vectors to produce a simulation result;
• a testing unit for testing said semiconductor integrated circuit device using said test vectors to produce a test result;
• a diagnosing unit for defining a first set of combinations of circuit elements based on said circuit data of said semiconductor integrated circuit device, said semiconductor integrated circuit device being composed of said circuit elements, for estimating a final set of failure candidates from said first set of combinations in a failure diagnosing process while reducing a number of combinations of said first set based on said simulation result and said test result for each of said test vectors;
• and
• an output unit for outputting said final set of failure candidates,
• wherein said diagnosing unit determines whether any functional fault is present, based on said test result for each of said test vectors, a process when it is determined that any functional fault is present for either one of said test vectors, and continues the failure diagnosing process when it is determined that any functional fault is not present for each of said test vectors,
• wherein said diagnoding unit performs a determining operationof a third set of combinations of said circuit element in which a failure does mot occur, based on said simulation result for a specifice test vector, and a removing operation of said third set of combinations from said first set of combinations to redefine said first set of combinations, and repeats said determining operation and said removing operation while changeng said specific test vector over at least a portion of said test vectors, and
• wherein said deagnosing unit further determines a third set of combinations of said circuit elements in which any failure does not occur, based on said simulation result for a specific test vector, when it is determined that the power source quiescent current fault is present, and calculates a product of said first set and said second set to redefine the calculating result as said first set when it is determined that the power source quiescent current fault is pressent.

A failure diagnosing apparatus for a semiconductor integrated circuit device, comprising:

• a circuit data storage unit for storing a circuit data of a semiconductor integrated circuit device;
• a test vector storage unit for storing test vectors for said semiconductor integrated circuit device;
• a simulating unit for simulating an operation of said semiconductor integrated circuit device using said test vectors to produce a simulation result;
• a testing unit for testing said semiconductor integrated circuit device using said test vectors to produce a test result;
• a diagnosing unit for defining a first set of combinations of circuit elements based on said circuit data of said semiconductor integrated circuit device, said semiconductor integrated circuit device being composed of said circuit elements, for estimating a final set of failure candidates from said first set of combinations in a failure diagnosing process while updating values corresponding to said combinations of said first set based on said simulation result and said test result for each of said test vectors;
• an output unit for outputting said final set of failure candidates;
• and
• a layout data storage unit for storing a layout data of said semiconductor integrated circuit device,
• wherein said diagnosing unit defines said first set of combinations of every two of said circuit elements based on said circuit data of said semiconductor integrated circuit device, selects combinations of said circuit elements based on said layout data of said semicomductor integrated circuit device such that any failure does not occur, to difine a second set of said selected combinations, and removes said seconds set from said first set to redefine said first set of combinations.