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AssigneeMotorola, Inc.
InventorsRami Natan, Arie Ben-Ephraim, Arie Kazachin, Alex Miretsky, Vitaly Sukonik
Estimating the term…
A computer and a method are described having multiple pointers for a branch instruction. A branch target instruction called by the branch instruction is divided into H parts locatable by K pointers. L of the K pointers are stored in the branch instruction and K-L pointers are stored with the H parts of the branch target instruction. A tag identifies a variable boundary between first and second halves of the memory, word by word. The first half of the memory space contains V of H parts of the instructions and the second half of the memory space contains the H-V parts. The parts in the first and second halves of the memory space are compressed and decompressed in parallel.
A computer system comprising a memory that stores a branch instruction and an associated branch target instruction, wherein each branch target instruction is divided into H parts identified by K pointers, wherein H(L) of the H parts correspond to L of the K pointers and H(K-L) of the H parts correspond to K-L of the K pointers, and the L pointers are with the branch instruction and point to the location of the H(L) parts and the K-L pointers are dispersed in association with the H(L) parts and some of the H(K-L) parts in the memory.
A method of operating a computer having memory and using a branch target instruction of H parts identified by K pointers, accessed by a related branch instruction, comprising:
Dependencies are inferred from the claim text.