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US 6,205,544 B1Granted
Decomposition of instructions into branch and sequential code sections
AssigneeIntel Corporation
InventorsJack D. Mills, Christopher B. Wilkerson
Life of this patent
Estimating the term…
Abstract
The decomposition of instructions into separate sequential and branch instruction code sections. In one embodiment, a system including a first store to store a first code section including only branch instructions and a second store to store a second code section including only sequential instructions. In another embodiment, the system also includes a processor having a first engine to process the branch instructions, and a second engine to process the sequential instructions.
Claims10
A system comprising:
- a first store to store a first code section including only branch instructions;
- a second store to store a second code section including only sequential instructions;
- and
- a processor comprising:
- a first engine to process the branch instructions of the first code section,
- a second engine to process the sequential instructions of the second code section, and
- a store to store a first interrupt instruction pointer pointing to a sequential instruction within the second code section and a second interrupt instruction pointer pointing to a branch instruction within the first code section.
4 more elements
A processor comprising:
- a first engine to process branch instructions of a first code section including only branch instructions, as retrieved from a first store storing only the first code section;
- a second engine to process sequential instructions of a second code section including only sequential instructions, as retrieved from a second store storing only the second code section;
- and
- a store to store a first interrupt instruction pointer pointing to a sequential instruction within the second code section and a second interrupt instruction pointer pointing to a branch instruction within the first code section.
1 more element
A method comprising
- compiling a source code into a first code section including only branch instructions and a second code section including only sequential instructions;
- processing the branch instructions of the first code section by a first processor engine;
- processing the sequential instructions of the second code section by a second processor engine;
- storing in a processor store a first interrupt instruction pointer pointing to a sequential instruction within the second code section;
- and
- storing in the processor store a second interrupt instruction pointer pointing to a branch instruction within the first code section.
3 more elements
Dependencies are inferred from the claim text.