Efficient handling of a large register file for context switching

A processor comprising:

• a plurality of functional units;
• a register file including a plurality of register file segments coupled to and associated with the plurality of functional units, respectively, the register file being divided into a plurality of register groups;
• a dirty bit register coupled to the register file;
• and
• a dirty bit logic coupled to the dirty bit register, the dirty bit logic having a connection for accessing a destination register (rd) field of an instruction and classifying the destination register rd according to the address in the rd field, the classification corresponding to a bit in the dirty bit register, the dirty bit logic evaluating the dirty bit register to designate that the particular classification includes a register that is written by the instruction.

A method of switching context in a processor that includes an executive storage for holding operand data operated upon by instructions executing on the processor, the executive storage being divided into a plurality of storage groups containing one or more storage elements, the method comprising:

• utilizing a dirty bit storage including a plurality of storage bits corresponding to a plurality of respective storage groups in the executive storage;
• receiving a destination address field of the executing instructions;
• responsive to an executed instruction, classifying a destination access as a targeted storage group according to information in the destination address field of the executed instruction;
• evaluating the classified destination based on whether the instruction updates the targeted storage group;
• and
• responsive to a context switch, saving storage groups based on the evaluation of the classified destinations.