Mechanism for dynamically adapting the complexity of a microprocessor

An adaptive hardware structure for a microprocessor, comprising a plurality of substantially identical elements coupled in segments of global address and data buses of said hardware structure;

• buffers connected between the elements to reduce segment delay in both of said buses, wherein each segment has substantially equal delay and is electrically isolated from its adjacent segments by said buffers so that individual element delays are independent of the number of other elements in said hardware structure, whereby the element delays are the same irrespective of the size of the structure;
• means for conditional reconfiguration of said hardware structure;
• a dynamic clock for setting processor clock speed of said microprocessor according to the configuration of said hardware structure for executing a current application;
• said data bus adapted to carry instructions to be executed by the microprocessor;
• wherein the magnitude of instructions issued per cycle relative to clock speed is variable according to the current configuration of the hardware structure.

A method for rendering a hardware structure for a microprocessor adaptive, comprising the steps of coupling a plurality of substantially identical elements in segments of global address and data buses of said hardware structure;

• connecting buffers between the elements to reduce segment delay in both of said buses, so that each segment has substantially equal delay and is electrically isolated from its adjacent segments by said buffers to render individual element delays independent of the number of other elements in said hardware structure, whereby the element delays are the same irrespective of the size of the structure;
• conditionally reconfiguring said hardware structure either by selectively disabling at least some of said elements while leaving the remaining elements enabled or by using primary and backup elements of respectively faster and slower elements and changing the boundary therebetween;
• setting processor clock speed of said microprocessor with a dynamic clock according to the number of said elements enabled or the status of the boundary between primary and backup elements, respectively, for executing a current application of said hardware structure;
• and issuing instructions to be executed by the microprocessor on said data bus, wherein the magnitude of instructions issued per cycle relative to clock speed is variable according to said number of elements enabled or said status of the boundary, respectively.