Branch instruction having different field lengths for unconditional and conditional displacements

An instruction to be executed by a central processing unit of a RISC type architecture, the central processing unit comprising a program counter, the instruction comprising:

• a conditional branch instruction of a first bit length and having a first area for a displacement that is used to obtain a destination address for a conditional branch, the destination address being calculated by adding the contents of the program counter to the displacement in the first area, the first area being of a second bit length;
• and
• an unconditional branch instruction of the first bit length and having a second area for a displacement that is used to obtain a destination address for an unconditional branch, the destination address being calculated by adding the contents of the program counter to the displacement in the second area, the second area being of a third bit length larger than the second bit length.

An instruction to be executed by a central processing unit which comprises a program counter, the instruction comprising:

• a conditional branch instruction of a first bit length and having a first area for a displacement that is used to obtain a destination address for a conditional branch, the destination address being calculated by adding the contents of the program counter to the displacement in the first area, the first area being of a second bit length;
• and
• an unconditional branch instruction of the first bit length and having a second area for a displacement that is used to obtain a destination address for an unconditional branch, the destination address being calculated by adding the contents of the program counter to the displacement in the second area, the second area being of a third bit length between the second bit length and the first bit length.

An instruction format to be executed by a central processing unit of a RISC type architecture and having a program counter, the instruction comprising:

• a conditional branch instruction being of a first bit length and having a first area for a displacement which is used for designating a destination address for a conditional branch when a condition matches and which indicates a relative distance from the contents of the program counter, the first area being of a second bit length smaller than the first bit length;
• and
• an unconditional branch instruction being of a first length and having a second area for a displacement which is used for designating a destination address for an unconditional branch and which indicates a relative distance from the contents of the program counter, the second area being of a third bit length smaller than the first bit length but larger than the second bit length.

A CPU, capable of processing at least one conditional branch instruction and at least one unconditional branch instruction, wherein:

• an instruction bit length of the conditional branch instruction is the same as that of the unconditional branch instruction, and
• a displacement length of the conditional branch instruction is different from that of the unconditional branch instruction.

A CPU, capable of processing at least one conditional branch instruction and at least one unconditional branch instruction, wherein:

• an instruction bit length of each of the conditional branch instruction and unconditional branch instruction is 16 bits, and
• a displacement length of the conditional branch instruction is smaller than that of the unconditional branch instruction.