Address translation unit supporting variable page sizes

An address translation unit for supporting a plurality of page modes, each having a different size, comprising:

• a tag interface means for receiving, from a linear address, data requested by a page mode supporting a highest page count among a plurality of page modes and for outputting effective tag data in response to a page mode select signal;
• a tag memory for storing the effective tag data from the tag interface means and for outputting a comparison signal after comparing the effective tag data with a previously stored tag data in response to a word signal and a write control signal;
• a data interface means for receiving, from a physical address, data requested by the page mode supporting the highest page count among the plurality of page modes and for outputting effective physical data in response to the page mode select signal;
• a data memory for storing the effective physical data from the data interface means and for outputting a converted physical address corresponding to the linear address in response to the word signal, the write control signal and the comparison signal;
• a decoder interface means for receiving a part of the linear address corresponding to an entry number in response to a page mode signal, and for outputting the part of the linear address as an entry index signal, wherein the entry number is a number supported by the address translation unit;
• a decoding means for decoding the part of the linear address from the decoder interface means and for outputting the word signal selecting an entry to the tag memory and the data memory in response to the entry index signal, the write control signal and a write way signal;
• page mode decoding means for decoding the page mode signal and for outputting the page mode select signal to the tag interface means and the data interface means, said page mode decoding means including,
• a NOR means for outputting a first control signal which represents a first page mode by NORing each bit of the page mode signal inputted from an external circuit;
• a first NAND means for outputting a second control signal which represents a second page mode by NANDing each bit of the page mode signal inputted from the external circuit;
• and
• a second NAND means for outputting a third control signal which represents a third page mode by NANDing an inverted least significant bit, and the remaining bits of the page mode signal inputted from the external circuit.