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US 6,205,523 B1Granted
Memory access with plural memories written with the same data
AssigneeMMC Networks, Inc.
InventorsAlexander Joffe, Ari Birger
Life of this patent
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AssigneeMMC Networks, Inc.
InventorsAlexander Joffe, Ari Birger
Estimating the term…
In a memory system, each data bus is connected to memories connected to different address buses. Each memory allows pipelined read operations such that when data are being read out from a memory in one read operation, the address can be provided to the memory for another read. However, write operations are not pipelined, and the write address and write data are provided to the memory simultaneously. Nevertheless, consecutive reads can overlap with writes. Each write operation uses address and data buses not taken by any read occurring in parallel with the write. The address and data buses are connected to the memories so that no data bus penalty occurs when a memory is switched from a read to a write or from a write to a read. In some embodiments, multiple memories are subdivided into sets of mirror-image memories. In each set, all the memories store the same data. When simultaneous read accesses are desired to read data stored in one of the memories, the read accesses can be performed instead to different memories that are mirror images of each other. When any memory is written, all the memories of the same set are written with the same data.
A method for accessing a plurality of sets of memories via N data buses, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the method comprising providing memory access allowing (i) a plurality of successive read operations to be performed immediately following one another, and at the same time, (ii) a plurality of successive write operations to be performed immediately following one another, wherein:
A method for accessing a plurality of sets of memories via N data buses, N being an even integer greater than or equal to 4, wherein each set of memories comprises N/2 memories, the method comprising:
A method for accessing a plurality of sets of memories by N first circuits, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the method comprising providing memory access allowing (i) a plurality of successive read operations to be performed immediately following one another, and at the same time, (ii) a plurality of successive write operations to be performed immediately following one another, wherein:
A method for accessing a plurality of sets of memories by N first circuits, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the method comprising:
An apparatus for providing access to a plurality of sets of memories via N data buses, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2, the apparatus comprising circuitry for allowing a plurality of successive read operations to be performed immediately following one another, and at the same time, a plurality of successive write operations to be performed immediately following one another, wherein:
An apparatus for providing access to a plurality of sets of memories via N data buses, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the apparatus comprising circuitry for:
An apparatus for providing N first circuits with access to a plurality of sets of memories, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the apparatus comprising circuitry for allowing a plurality of successive read operations to be performed immediately following one another, and at the same time, a plurality of successive write operations to be performed immediately following one another, such that:
An apparatus for providing N first circuits with access to a plurality of sets of memories, N being an even integer greater than or equal to 4, wherein each set of memories comprises at least N/2 memories, the apparatus comprising circuitry for:
Dependencies are inferred from the claim text.