Method and apparatus for implementing non-temporal stores
AssigneeIntel Corporation
InventorsSalvador Palanca, Vladimir Pentkovski, Steve Tsai, Subramaniam Maiyuran
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Abstract
A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
Claims19
A processor comprising:
- a decoder to decode instructions and to identify a first instruction as being associated with a first write back or write through non-temporal store, a non-temporal store comprising data that is to be utilized by the processor no more than a limited amount of number of times within a predetermined period;
- and
- a circuit, in response to the decoded first instruction, to,
- detect the first write back or write through non-temporal store that misses a cache, and
- allocate a buffer for the first write back or write through non-temporal store in write combining mode.
A method for implementing non-temporal stores in a processor, the method comprising:
- detecting a first instruction associated with a first write-back or write-through store;
- determining whether the first write-back or write-through store is temporal or non-temporal, a temporal store comprising data that is likely to be utilized repeatedly within a predetermined period, a non-temporal store comprising data that is likely to be utilized no more than a few times within the predetermined period;
- determining whether the first write-back or write-through store hits or misses the cache closest to the processor;
- if the first write-back or write-through is non-temporal and misses the cache, allocating a buffer in write combining mode;
- and
- writing the first write-back or write-through store in the buffer.
A method for implementing non-temporal stores in a processor, the method comprising:
- detecting an instruction associated with a non-temporal write-back store;
- determining that the non-temporal write-back store hits on a non-write combining fill buffer;
- merging the non-temporal write-back store with the non-write combining fill buffer if one of the following conditions is met,
- a) the non-write combining fill buffer is currently servicing a write-back store,
- b) the non-write combining fill buffer is globally observed in the modified state, and
- c) the non-write combining fill buffer is globally observed in the exclusive state and the buffer is ready to write the data contained within the buffer to the cache level closest to the processor.
A method for implementing non-temporal stores in a processor, the method comprising:
- detecting an instruction associated with a non-temporal write-through store;
- determining that the non-temporal write-through store hits on a non-write combining fill buffer;
- merging the non-temporal write-through store with the non-write combining fill buffer if one of the following conditions is met,
- a) the non-write combining fill buffer is currently servicing a write-back store,
- b) the non-write combining fill buffer is globally observed in the modified state.
Dependencies are inferred from the claim text.