Cache management for a multi-threaded processor
AssigneeHewlett-Packard Company
InventorsRobert Aglietti, Rajiv Gupta
Life of this patent
Estimating the term…
Abstract
A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.
Claims16
A method for managing a cache memory for a multi-threaded processor, comprising the steps of:
- partitioning the cache memory into a set of separate partitions and allocating a separate subset of the partitions to each of a set of threads of the multi-threaded processor;
- performing a cache lookup operation to the cache memory in response to an access to a data line by the multi-threaded processor;
- if a cache miss occurs, then selecting a replacement line in one of the partitions of the cache memory which is allocated to a particular one of the threads from which the access originated wherein the partitioning of the cache memory is static.
A method for managing a cache memory for a multi-threaded processor, comprising the steps of:
- partitioning the cache memory among the threads of the multi-threaded processor;
- performing a cache lookup operation to the cache memory in response to an access to a data line by the multi-threaded processor;
- if a cache miss occurs, then selecting a replacement line in a partition of the cache memory which is allocated to a particular thread of a set of threads of the multi-threaded processor from which the access originated wherein the step of partitioning the cache memory includes the step of specifying a threshold value for each thread wherein each threshold value indicates a maximum number of a set of ways of the cache memory which may be used by the corresponding thread.
A computer system, comprising:
- processor that executes a set of threads;
- cache memory which is partitioned into a set of separate partitions wherein a separate subset of the partitions is allocated to each of the threads such that a cache miss to a data line which is associated with a particular thread causes a replacement line in the cache memory to be selected from one of the partitions of the cache memory that is allocated to the particular thread wherein the partitions among the threads is hard-wired in the cache memory.
A computer system, comprising:
- processor that executes a set of threads;
- cache memory which is partitioned among the threads such that a cache miss to a data line which is associated with a particular thread causes a replacement line in the cache memory to be selected from a partition of the cache memory that is allocated to the particular thread wherein the cache memory is an n-way cache memory and the cache memory includes a set of allocation threshold registers which specify a maximum number of the n-ways of the cache memory that may be used by each thread.
Dependencies are inferred from the claim text.