Main memory control apparatus for use in a memory having non-cacheable address space allocated to DMA accesses

A method of controlling data access to a main memory in a computer system having a CPU incorporating a cache memory, an access enable device capable of making direct memory access to a main memory, said main memory including a first address area allocated as an address area from which data is loaded into said cache memory in said CPU but inhibiting data access from said access enable device to said first address area, and a second address area allocated as an address area to which data is accessed from said access enable device but inhibiting data from being loaded into said cache memory in said CPU from said second address area, a read buffer memory storing data stored in said second address area and transferring the stored data in response to a data access request from said CPU or access enable device to said CPU or access enable device issuing the read request, and a write buffer memory storing data to be written into said main memory from said CPU or access enable device, comprising the steps of:

• when said CPU or access enable device issues a data read request, carrying out control in such as to, retrieve said read buffer memory, if data to be read exists in said read buffer memory, transfer said data in said read buffer memory to said CPU or access enable device issuing the read request;
• retrieve said write buffer memory, if data to be read does not exist in said read buffer memory, and if data to be read exists in said write buffer memory, transfer said data in said write buffer memory to said CPU or access enable device issuing the read request;
• and
• read from said second address area data at addresses different from the address under the read request from said CPU or access enable device only in lower bits of fixed length, if data to be read does not exist in said write buffer memory, and load the read data into said read buffer memory while transferring the read data to said CPU or access enable device issuing the read request.

A main memory control apparatus for use in a computer system having main memory, a CPU incorporating a cache memory, and an access enable device capable of making direct memory access to said main memory, said main memory including a first address area allocated as an address area from which data is loaded into said cache memory in said CPU but inhibiting data access from said access enable device to said first address area, and a second address area allocated as an address area to which data is accessed from said access enable device but inhibiting data from being loaded into said cache memory in said CPU from said second address area, said main memory control apparatus controlling data access to said main memory comprising:

• a read buffer memory storing data stored in said second address area;
• a plurality of write buffer memories storing data to be written into said main memory from said CPU or access enable device;
• and
• a control portion operating, when said CPU or access enable device issues a data write request, in such a manner that:
• said control portion retrieves said read buffer memory, if data exists in said read buffer memory's address requested by said data write request, said control portion nullifies data in said read buffer memory, and retrieves said write buffer memory having data address different from the address under the write request only in lower bits of fixed length, if said write buffer memory having said data address exists, said control portion writes data requested to be written into said write buffer memory having said data address, if said write buffer memory having said data address does not exist, said control portion writes said data requested to be written into an empty write buffer memory.

A method of controlling data access to a main memory in a computer system having a CPU incorporating a cache memory, an access enable device capable of making direct memory access to a main memory, said main memory including a first address area allocated as an address area from which data is loaded into said cache memory in said CPU but inhibiting data access from said access enable device to said first address area, and a second address area allocated as an address area to which data is accessed from said access enable device but inhibiting data from being loaded into said cache memory in said CPU from said second address area, a read buffer memory storing data stored in said second address area, and a plurality of write buffer memories storing data to be written into said main memory from said CPU or access enable device, comprising the steps of:

• retrieving said read buffer memory when said CPU or access enable device issues a data write request, if data exists in said read buffer memory's address requested by said data write request, nullifying data in said read buffer memory;
• retrieving a write buffer memory having data address different from the address under the write request only in lower bits of fixed length;
• writing data requested to be written into said write buffer memory having said data address when said data address exists in said write buffer memory;
• and
• writing data requested to be written into an empty write buffer memory when said write buffer memory having said data address does not exist.