Synchronous SRAM having global write enable

A system comprising:

• a processor;
• cache control logic connected to the processor;
• and
• a synchronous SRAM connected to the cache control logic and to the processor, the SRAM including:
• an SRAM core having a memory array of a plurality of bytes, having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers;
• a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation;
• a plurality of data inputs organized into bytes and connected to the processor;
• a global write input connected to the cache control logic;
• global write sway circuitry connecting the global write input to the byte write registers and selectively causing all bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the global write input;
• and
• a byte write enable input, a plurality of byte write inputs, and byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs, wherein individual bytes are selectably written to, but multiple bytes are simultaneously selected when it is desired to read from the bytes.

A synchronous SRAM comprising:

• an SRAM core having a memory array of a plurality of bytes, having a plurality of byte write drivers, having sense amplifiers, and having I/O buffers;
• a plurality of data inputs organized into bytes;
• a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array;
• a byte write enable input;
• a plurality of byte write inputs;
• byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs;
• and
• a global write input, and global write circuitry connecting the global write input to the byte write registers, all bytes of the data inputs being written into the SRAM core in response to a predetermined asserted logic level being present on the global write input, without need for assertion of a predetermined logic level on another input to cause all bytes of the data inputs to be written into the SRAM core.

A system comprising:

• a processor including a plurality of byte enable outputs;
• control logic communicating with the processor;
• a first synchronous SRAM communicating with the processor and the control logic, the first SRAM comprising:
• an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers;
• address control circuitry for accessing a selected location of the memory array within the SRAM core;
• a plurality of byte write registers respectively connected to the write drivers, the byte write registers selectively activating corresponding byte write drivers to input data into the memory array during a write operation;
• a plurality of data inputs organized into bytes;
• is a byte write enable input;
• a plurality of byte write inputs respectively directly connected to the byte enable outputs of the processor;
• byte write enable circuitry connecting the byte write inputs and the byte write enable input to the byte write registers and selectively causing individual bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the byte write enable input and also depending on the asserted logic level on the individual byte write inputs, wherein individual bytes are selectably written to, but multiple bytes are simultaneously selected when it is desired to read from the bytes;
• a global write input, and global write only circuitry connecting the global write input to the byte write registers and selectively causing all bytes of the data inputs to be written into the SRAM core when a predetermined asserted logic level is present on the global write input, without need for assertion of a predetermined logic level on any other input to cause all bytes of the data inputs to be written into the SRAM core;
• first, second, and third chip enable inputs for receiving at least a module enable signal and a memory select enable signal;
• a device control circuit connected to the SRAM core and the chip enable inputs, the device control circuit performing the dual functions of selectively enabling or disabling the first SRAM and selectively permitting access to the SRAM core when the first SRAM is enabled in accordance with the module enable signal and the memory select enable signal;
• and
• a second synchronous SRAM communicating with the processor and the control logic, the second SRAM comprising:
• an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers;
• address control circuitry for accessing a selected location of the memory array within the SRAM core;
• first, second, and third chip enable inputs for receiving at least the module enable signal and a memory select enable signal;
• a device control circuit connected to the SRAM core and the chip enable inputs, the device control circuit performing the dual functions of selectively enabling or disabling the second SRAM and selectively permitting access to the SRAM core when the second SRAM is enabled in accordance with the module enable signal and the memory select enable signal;
• the memory select enable signal selecting the first SRAM when the memory select enable signal is at one asserted logic level and selecting the second SRAM when the memory select enable signal is at another asserted logic level;
• and
• the module enable signal enabling operation of both SRAMs when the module enable signal is at one asserted logic level and disabling operation of both SRAMs when the module enable signal is at another asserted logic level.