Back to results
US 6,205,512 B1Granted
Set of two memories on the same monolithic integrated circuit
AssigneeSGS-Thomson Microelectronics S.A.
InventorsAlessandro Brigati, Jean Devin, Bruno Leconte
Life of this patent
Estimating the term…
Abstract
Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.
Claims31
A monolithic integrated circuit comprising:
- first and second memories that are distinct from each other;
- a selection circuit for selecting either of the first and second memories in response to receiving a selection signal;
- and
- first and second microcontrollers respectively linked to the first and second memories for sequencing write or read operations in the first and second memories, wherein each microcontroller includes a circuit for the execution in each memory of the write or read operations independently of the value of the selection signal;
- wherein the data stored in the first and second memories is at least one of the same and different type;
- wherein each microcontroller is connected to the selection circuit by means for generating a time delay signal of a given duration, the time delay signal being activated when one of said memories is selected, wherein the time delay signal prompts a hold signal during this given duration, the given duration being greater than or equal to a duration of an execution of a read operation or a write operation.
3 more elements
A monolithic integrated circuit comprising:
- a selection circuit for selecting either of the first and second memories in response to receiving a selection signal;
- first and second microcontrollers respectively linked to the first and second memories for sequencing write or read operations in the first and second memories, wherein each microcontroller includes a circuit for the execution in each memory of the write or read operations independently of the value of the selection signal;
- and
- wherein each microcontroller is connected to the selection circuit by means for generating a time delay signal of a given duration, the time delay signal being activated when one of said memories is selected, wherein the time delay signal prompts a hold signal during this given duration, the given duration being greater than or equal to a duration of an execution of a read operation or a write operation.
1 more element
A monolithic integrated circuit comprising:
- a selection circuit for selecting either of the first and second memories in response to receiving a selection signal;
- first and second mircocontrollers respectively linked to the first and second memories for sequencing write or read operations in the first and second memories, wherein each microcontroller includes a circuit for the execution in each memory of the write or read operations independently of the value of the selection signal;
- and
- a circuit for assuring that the selection signals are complementary so that only one memory will be selected at a time.
1 more element
A monolithic integrated circuit comprising:
- a selection circuit for selecting either of the first and second memories in response to receiving a selection signal;
- first and second microcontrollers respectively linked to the first and second memories for sequencing write or read operations in the first and second memories, wherein each microcontroller includes a circuit for the execution in each memory of the write or read operations independently of the value of the selection signal;
- and
- a plurality of duplicated load pumps for biasing lines in each of the memories independently of one another.
1 more element
A monolithic integrated circuit further comprising:
- a selection circuit for selecting either of the first and second memories in response to receiving a selection signal;
- first and second microcontrollers respectively linked to the first and second memories for sequencing write or read operations in the first and second memories, wherein each microcontroller includes a circuit for the execution in each memory of the write or read operations independently of the value of the selection signal;
- and
- an OR gate at an enabling input of each microcontroller for receiving the hold signal, and for generating a holding signal at the enabling input during a write or read operation.
1 more element
Dependencies are inferred from the claim text.