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US 6,205,511 B1Granted
SDRAM address translator
AssigneeNational Semiconductor Corporation
InventorSheung-Fan Wen
Life of this patent
Estimating the term…
Abstract
A buffer manager divides a memory space into a plurality of buffers. Each buffer occupies a plurality of sequential memory locations. The sequential memory locations include a start and an end address. To write data to a buffer, the buffer manager provides a start address and burst size to an address translator. The address translator converts the start address and the burst size to SDRAM memory address locations. The start and end address of each buffer is mapped to a different bank in the SDRAM memory.
Claims27
An address translation circuit for mapping address information to an SDRAM, comprising:
- a buffer manager interface that receives address information from a buffer manager, wherein the buffer manager allocates a plurality of buffers each having a start address and an end address related therewith;
- and
- a translation circuit operationally coupled with the buffer manger interface to map the start address of each of the plurality of buffers to a first bank and to map the related end address to a second bank, different than the first bank,
- and wherein the translation circuit includes an adder that adds the start address and a burst size address to generate the end address.
1 more element
A circuit configured to translate an address comprising:
- a start address bus that receives a start address defined in a flat address space;
- a burst size bus that receives a burst size;
- a first page start address bus that provides a first page start address in an SDRAM address space;
- a first page end address bus that provides a first page end address in an SDRAM address space;
- a second page start address bus that provides a second page start address in an SDRAM address space;
- a second page end address bus that provides a second page end address in an SDRAM address space;
- and
- a translation circuit operationally coupled with the start address bus and the burst size bus to receive the start address and the burst size, and operationally coupled with the first page start address bus, the first page end address bus, the second page start address bus and the second page end address bus to provide the first page start address, the first page end address, the second page start address and the second page end address, wherein when the burst size exceeds a determined page size, the translation circuit generates the first page start address and the first page end address in a first page and generates the second page start address and the second page end address in a second page, wherein the first and second pages are in different banks, and wherein the translation circuit comprises an adder operationally coupled with the start address bus and the burst size bus and adds the burst size to the start address to generate an end address.
5 more elements
A circuit comprising:
- a memory having a plurality of banks, each bank having a plurality of pages, wherein a first page in a first bank may be accessed simultaneous to precharging a second page in a second bank;
- an address bus for accessing the memory, wherein the memory is divided into a plurality of buffers so that each buffer has a start address, a plurality of sequential address locations and an end address, and wherein each buffer is sized to hold a packet of data;
- and
- a translation circuit operationally coupled between the memory and the address bus, wherein the translation circuit maps a start address of a first buffer to the first page in the first bank, maps an end address of the first buffer to the second page in the second bank, and maps a start address of a second buffer to the second bank, and maps an end address of the second buffer to the first bank,
- and wherein the translation circuit includes an adder that adds the start address and the burst size to generate the end address.
2 more elements
A method of operating a memory comprising the steps of:
- receiving a start address and a burst size, wherein the burst size is greater than a page size;
- translating the start address to a first page start address on a first page of memory;
- selecting a second page start address on a second page of memory;
- determining the end address based upon the start address and the burst size;
- writing data to the first page of memory;
- and
- precharging the second page of memory simultaneous to the step of writing data.
4 more elements
Dependencies are inferred from the claim text.