System for compressing video data using bi-orthogonal wavelet coding having a DSP for adjusting compression ratios to maintain a constant data flow rate of the compressed data

Apparatus for encoding video data representing an image, comprising:

• a video encoder for receiving said video data, said video encoder compressing said video data using a compression algorithm having a bi-orthogonal (7,9) wavelet transform to generate compressed video data;
• a random access memory connected to said video encoder, said random access memory operating as a temporary storage device for storing said compressed video data whenever said video encoder is compressing said video data;
• a digital signal processor connected to said video encoder, said digital signal processor monitoring a data flow rate of said compressed video data from said video encoder, said digital signal processor adjusting compression ratios for said video encoder to maintain a constant data flow rate of said compressed video data from said video encoder;
• a programmed read only memory connected to said digital signal processor, said programmed read only memory containing software for said digital signal processor, said software enabling operation of said digital signal processor;
• and
• a programmed gate array connected to said video encoder to receive said compressed video data, said programmed gate array converting said compressed video data from a parallel format to a serial format for transmission to an external processor, said programmed gate array maintaining a constant serial data flow rate of said compressed video data to said external processor
• said video encoder having a data storage means connected to said programmed gate array, said data storage means storing said compressed video data prior to said video encoder providing said compressed video data to said programmed gate array;
• said programmed gate array including a flush data controller connected to said data storage means;
• said video encoder providing a service request signal to said programmed gate array whenever an overflow condition of said compressed video data is about to occur within said data storage means;
• and
• said flush data controller, responsive to said service request signal, flushing excess compressed video data from said data storage means whenever said overflow condition occurs within said data storage means.

Apparatus for encoding video data representing an image, comprising:

• a video encoder for receiving said video data, said video encoder compressing said video data using a compression algorithm having a bi-orthogonal (7,9) wavelet transform to generate compressed video data;
• a random access memory connected to said video encoder, said random access memory operating as a temporary storage device for storing said compressed video data whenever said video encoder is compressing said video data;
• a digital signal processor connected to said video encoder, said digital signal processor monitoring a data flow rate of said compressed video data from said video encoder, said digital signal processor adjusting compression ratios for said video encoder to maintain a constant data flow rate of said compressed video data from said video encoder;
• a programmed read only memory connected to said digital signal processor, said programmed read only memory containing software for said digital signal processor, said software enabling operation of said digital signal processor;
• and
• a programmed gate array connected to said video encoder to receive said compressed video data, said programmed gate array converting said compressed video data from a parallel format to a serial format for transmission to an external processor, said programmed gate array maintaining a constant serial data flow rate of said compressed video data to said external processor
• said video encoder having a FIFO connected to said programmed gate array, said FIFO storing said compressed video data prior to said video encoder providing said compressed video data to said programmed gate array;
• said programmed gate array including a flush data controller connected to said FIFO;
• said video encoder providing a service request signal to said programmed gate array whenever an overflow condition of said compressed video data is about to occur within said FIFO;
• said flush data controller, responsive to said service request signal, flushing excess compressed video data from said FIFO whenever said overflow condition occurs within said FIFO;
• said video encoder providing a FIFO stop signal to the gate array whenever said FIFO is empty;
• said programmed gate array, responsive to said FIFO stop signal setting a FIFO_MASK flag to a predetermined logic state t0 prevent a read operation of said FIFO within said video encoder, said programmed gate array generating dummy video data blocks and then transmitting said dummy video data blocks to said external processor whenever said overflow condition occurs within said FIFO.