Data processor with bit unstuffing instruction set extension

An apparatus comprising a computer readable medium having a processor recorded thereon, the processor comprising:

• a first input receiving data;
• a second input receiving a zero unstuffing instruction;
• a logic unit coupled to the first input and the second input, the logic unit including activatible zero unstuffing circuitry which is activated upon receipt of the zero unstuffing instruction and which unstuffs the data to produce modified data;
• an output coupled to the logic unit, the output outputting the modified data;
• and
• wherein the processor can be reprogrammed to execute one of many different instructions.

A method of processing data in a processor comprising the steps of:

• receiving input data at a processor, which processor is programmable to execute one of many different instructions;
• receiving, separately from the input data, a zero unstuffing instruction at the processor;
• coupling the input data to a logic unit within the processor, the logic unit including activatible zero unstuffing circuitry;
• activating zero unstuffing circuitry in the logic unit upon the receipt of the zero unstuffing instruction;
• unstuffing the data to produce modified data;
• and
• outputting the modified data.