Fast 2-input 32-bit domino adder
AssigneeIntel Corporation
InventorsRajesh Manglore, Sudarshan Kumar
Life of this patent
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Abstract
In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.
Claims18
An adder comprising:
- a first block in a first half of the adder to generate at least two sum bits and a section carry signal, the at least two sum bits and the section carry signal being generated in parallel;
- a second block in a second half of the adder to generate at least two additional sum bits, a corresponding block carry signal and corresponding group generate and group propagate signals of the block;
- and
- a third block in the second half of the adder to receive the section carry signal and the corresponding block carry signal, the third block including (i) a carry processor to process the section carry signal and to output a second block carry signal corresponding to the third block, and (ii) a sum selector to generate a sum bit from the corresponding group generate and group propagate signals, the second block carry signal and the sum bit being generated in parallel.
Implemented in a section of an adder including a plurality of circuit blocks, a circuit block comprising:
- a first sum selector to receive a first group generate signal, a first group propagate signal, and a block carry signal to generate a first sum bit;
- a second sum selector to receive a second group generate signal, a second group propagate signal and the block carry signal to generate a second sum bit, the second sum selector operating in parallel with the first sum selector;
- and
- a carry processor to receive a section carry signal and group generate and group propagate signals from at least two of the plurality of circuit blocks in the section other than the circuit block, the carry processor to compute a carry for the circuit block, the carry processor to operate in parallel with the first sum selector and the second sum selector.
A method of adding two binary numbers comprising:
- generating at least two sum bits and a section carry signal, the at least two sum bits and the section carry signal being generated in parallel;
- generating at least two additional sum bits, a block carry signal, a group generate and group propagate signals;
- receiving the block carry signal and the section carry signal;
- and
- generating a second block carry signal corresponding to the third block using the section carry signal.
Dependencies are inferred from the claim text.