US 6,205,461 B1 · Floating point arithmetic logic unit leading zero count using fast approximate rounding

Abstract

A floating point arithmetic logic unit includes two rounding units that select between an incremented, unincremented, and complemented result from a carry propagate adder. A fast rounding unit selects a result as an approximation based on the equality or inequality of the exponents of the operands, the relative sizes of the mantissas and the presence of a guard bit. The result selected by the fast rounding unit is received by a leading zero count unit, which counts the leading zeros of the result. A second slower rounding unit meanwhile makes a selection between the incremented, unincremented, and complemented results based on the rounding mode, the sign of the result and whether the result is exact. The result is inexact when both the most significant bit and the guard bit are equal to one. While the slower rounding unit may take longer to determine the appropriate selection, the result selected is the most accurate. Based on the number of leading zeros determined from the result selected by the fast rounding unit, the bits in the result selected by the slower rounding unit are left shifted thereby normalizing the result.

Claims15

Dependent claims

A floating point unit comprising:

a register file;
a carry propagate adder coupled to said register file, wherein said carry propagate adder generates an incremented result and an unincremented result;
an inverter coupled to said carry propagate adder, wherein said inverter generates a complemented unincremented result;
a first select unit coupled to said carry propagate adder and said inverter and a second select unit coupled to said carry propagate adder and said inverter, wherein said incremented result, said unincremented result, and said complemented unincremented result are received by both said first select unit and said second select unit;
a first rounding unit coupled to said first select unit, wherein said first rounding unit selects between said incremented result, said unincremented result, and said complemented unincremented result from said first select unit;
a second rounding unit coupled to said second select unit, wherein said second rounding unit selects between said incremented result, said unincremented result, and said complemented unincremented result from said second select unit;
a leading zero count unit coupled to said first select unit;
and
a shifting unit coupled to said second select unit and controlled by said leading zero count unit.

6 more elements

A method of counting the leading zeros in a result in a floating point unit, said method comprising:

generating an incremented result, an unincremented result, and a complemented unincremented result of the subtraction of two operands;
making a first selection from said incremented result, said unincremented result, and said complemented unincremented result;
making a second selection from said incremented result, said unincremented result, and said complemented unincremented result;
counting the leading zeros in said first selection;
and
shifting said second selection by an amount based on the number of said leading zeros in said first selection.

3 more elements

Dependencies are inferred from the claim text.

Floating point arithmetic logic unit leading zero count using fast approximate rounding

Life of this patent

Floating point arithmetic logic unit leading zero count using fast approximate rounding

Life of this patent

Abstract

Claims15