Back to results
US 6,205,459 B1Granted
Digital signal processor and digital signal processing system incorporating same
AssigneeYamaha Corporation
InventorAkira Sogo
Life of this patent
Estimating the term…
Abstract
There is provided a digital signal processor. A bus transfers data to be processed by an arithmetic operation unit and results of arithmetic processing by the arithmetic operation unit. At least one accumulator holds the results of the arithmetic processing by the arithmetic operation unit and delivers the results to the bus. A bypass device delivers the results by bypassing the at least one accumulator.
Claims12
A digital signal processor comprising:
- an arithmetic operation unit having an output bit width of N;
- a bus of bit width M that transfers data to be processed by said arithmetic operation unit and results of arithmetic processing by said arithmetic operation unit, wherein M<N;
- at least one accumulator that holds said results of said arithmetic processing by said arithmetic operation unit and delivers said results to said bus, wherein said at least one accumulator has a bit storage capacity N;
- and
- a bypass device that delivers said results to said bus by bypassing said at least one accumulator, wherein said bypass device comprises a delay element that delays delivery of said results of said arithmetic processing by said arithmetic operation unit to said bus, said delay element delivering said results to said bus at a same timing that said results are delivered by way of said at least one accumulator, and wherein said delay element has a bit storage capacity M.
2 more elements
A digital signal processor comprising:
- an arithmetic operation unit having an output bid width N;
- a bus of bit width M that transfers data to be processed by said arithmetic operation unit and results of arithmetic processing by said arithmetic operation unit, wherein M<N;
- at least one accumulator that holds said results of said arithmetic processing by said arithmetic operation unit and delivers said results to said bus, wherein said accumulator has a bit storage capacity N;
- and
- a bypass device that delivers said results by bypassing said at least one accumulator, wherein said bypass device comprises a delay element that delays delivery of said results of said arithmetic processing by said arithmetic operation unit to said bus, said delay element delivering said results to said bus at a same timing that said results are delivered by way of said at least one accumulator, and wherein said delay element has a bit storage capacity M.
2 more elements
A digital signal processor comprising:
- an arithmetic operation unit having an output bid width N;
- a bus of bit width M that transfers data to be processed by said arithmetic operation unit and results of arithmetic processing by said arithmetic operation unit, wherein M<N;
- at least one accumulator that holds said results of said arithmetic processing by said arithmetic operation unit and delivers said results to said bus, wherein said at least one accumulator has a bit storage capacity N;
- and
- a bypass device that delivers said results to said bus by bypassing said at least one accumulator, wherein said bypass device comprises a delay element that delays delivery of said results of said arithmetic processing by said arithmetic operation unit to said bus, and wherein said delay element has a bit storage capacity M.
2 more elements
A digital signal processor comprising:
- an arithmetic operation unit having an output bit width N;
- a bus of bit width M that transfers data to be processed by said arithmetic operation unit and results of arithmetic processing by said arithmetic operation unit, wherein M<N;
- at least one accumulator that holds said results of said arithmetic processing by said arithmetic operation unit and delivers said results to said bus, wherein said accumulator has a bit storage capacity N;
- and
- a bypass device that delivers said results by bypassing said at least one accumulator, wherein said bypass device comprises a delay element that delays delivery of said results of said arithmetic processing by said arithmetic operation unit to said bus, and wherein said delay element has a bit storage capacity M.
2 more elements
Dependencies are inferred from the claim text.