System and method for minimizing clock cycles lost to overhead data in a video decoder

In a video processing device, circuitry comprising:

• an encoder for generating first and second groups of overhead bits, the first group comprising a fixed number of overhead bits and the second group comprising a variable number of overhead bits, said overhead bits comprising data representing (a) a difference between maximum and minimum pixel values within a block of pixels, (b) a minimum pixel value within the block of pixels, and (c) a difference between the minimum pixel value and a first pixel value within the block of pixels;
• a shift register for receiving pixel data from a data source, receiving the second group of overhead bits from the encoder, and providing output of the pixel data and the second group of overhead bits;
• and
• a multiplexer for receiving the pixel data and the second group of overhead bits from the shift register, receiving the first group of overhead bits from the encoder, and providing output of the pixel data and the first and second groups of overhead bits.