Phase control circuit, semiconductor device and semiconductor memory

A semiconductor device, comprising:

• a clock input circuit which receives an external clock signal therein to thereby generate an internal clock signal;
• an internal circuit activated in synchronism with the internal clock signal;
• an output circuit which outputs the result of operation of said internal circuit to the outside;
• and
• a clock reproducing circuit for matching the phase of output operation by said output circuit with that of the external clock signal,
• said clock reproducing circuit including,
• first and second predetermined delay circuits which respectively add predetermined delay times to a reference clock signal synchronized with the internal clock signal and are connected to each other in series form;
• a phase difference detection circuit which detects the difference in phase between the output of said second predetermined delay circuit and the reference clock signal;
• a first phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to an output clock signal of said first predetermined delay circuit;
• a plurality of fixed delay circuits which respectively receive a first clock signal outputted from said first phase difference reproduction circuit therein and add predetermined delay times different from one another to the input first clock signal;
• a detection circuit which receives clock signals outputted from said plurality of fixed delay circuits and the reference clock signal therein and generates detected signals represented in plural bits each corresponding to the difference in phase between the reference clock signal and the first clock signal;
• a second phase difference reproduction circuit which adds the phase difference detected by said phase difference detection circuit to the reference clock signal;
• and
• a variable delay circuit which receives said detected signals represented in a plurality of bits in parallel from said detection circuit and adds a delay in the phase difference corresponding to said each input detected signal to a clock signal outputted from said second phase difference reproduction circuit;
• and
• wherein said output circuit allows the phase of the output operation to coincide with that of the external clock signal in synchronism with a clock signal outputted from said variable delay circuit.

A signal generating circuit, comprising:

• a control circuit which compares each of a plurality of signals different in change timing from one another with a signal in a predetermined cycle of a reference clock signal to thereby output a detected signal;
• and
• an output circuit which outputs a signal corresponding to the reference clock signal, based on the detected signal;
• and
• a plurality of delay circuits respectively provided with delay time control units, and
• wherein each individuals of said plurality of delay circuits are first delay circuits provided within said output circuit,
• said plurality of other delay circuits excluding said plurality of first delay circuits are a plurality of second delay circuits provided within said control circuit,
• said plurality of second delay circuits respectively output said plurality of signals different in change timing from one another in response to a common input signal, and
• each of delay control units of said first delay circuits is variably controlled based on the detected signal.