Burst mode flash memory
AssigneeFujitsu Limited
InventorTakao Akaogi
Life of this patent
Estimating the term…
Abstract
A clock generator circuit in response to an external output enable signal generates an internal clock signal that is delayed to increase the reliability of the data outputted from the flash memory. A clock trigger generator circuit by decoding address signals generates an internal clock signal to reduce the latency time of the output of data with respect to the external clock signal. A bypass signal is provided to disable the clock trigger generator circuit. An output circuit provides a bypass data path to additionally reduce the latency time of the outputting of data for a burst mode flash memory. A decoder counter selector circuit provides a “look-ahead” address decoding scheme to reduce the time needed to output data.
Claims7
A burst mode flash memory device synchronously operating with an external clock, the burst mode flash memory device comprising:
- a memory cell array having a plurality of memory cells, each memory cell storing data;
- input circuits for selecting a subset of memory cells from the plurality of memory cells and generating an internal clock that is synchronized to the external clock, the input circuits including delay circuitry for delaying generation of the internal clock for at least one clock period upon receipt of predefined control signal;
- reader circuits fetching data stored in the subset of memory cells selected;
- and
- output circuits outputting the data fetched in a predetermined grouping and synchronously with the internal clock, such that the input circuits upon receipt of a predefined control signal, the generation of the internal clock is delayed for at least one clock period.
In a flash memory device having a memory cell array, an address decoder for processing address information used in accessing the memory cell array, a method of increasing reliability of access of the memory cell array, the method comprising:
- receiving an output enable signal;
- forming a delayed output enable signal by delaying the output enable signal a plurality of clock cycles;
- providing the delayed output enable signal to an internal clock generator, the delayed output enable signal being used to enable an internal clock signal;
- and
- generating the internal clock signal for use in accessing the memory cell array based on the delayed output enable signal.
A flash memory device including a memory cell array, an address signal generator generating address signals for an address decoder, a clock buffer for generating an internal clock signal based on an external clock signal, and handshake circuit comprising a comparator which compares least significant address signals generated by the address signal generator and forms a control signal based on the comparison, a shift circuit for phase shifting the external clock signal and thereby forming a shifted clock signal, and a gate circuit for. gating the shifted clock signal using the control signal, whereby the shifted clock signal is used by the clock buffer in generating the internal clock signal.
Dependencies are inferred from the claim text.