LSI device with memory and logics mounted thereon
AssigneeFujitsu Limited
InventorsHiroyoshi Tomita, Yasurou Matsuzaki, Masao Taguchi
Life of this patent
Estimating the term…
Abstract
A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.
Claims20
An LSI device on which a first chip and a second chip to be connected by lead lines are mounted,
- said first chip having an output circuit for outputting a data signal in response to an output clock, and a data output terminal connected to said output circuit,
- said second chip having an input circuit receiving said data signal, output from said output circuit, in response to a transfer clock generated from said output clock and sent to said second chip via a lead line for clock, and a data input terminal connected to said input circuit,
- said data output terminal in said first chip and said data input terminal in said second chip being arranged on opposing sides of both chips and being connected together via a lead line for data.
An LSI device on which a first chip and a second chip to be connected by lead lines are mounted,
- said first chip having an input circuit for inputting a data signal from said second chip in response to a transfer clock in said first chip, and a data input terminal connected to said input circuit,
- said second chip having an output circuit for outputting a data signal in said second chip to said input circuit in response to an output clock generated from said transfer clock and sent to said second chip via a lead line for clock, and a data output terminal connected to said output circuit,
- said data input terminal in said first chip and said data output terminal in said second chip being arranged on opposing sides of both chips and being connected together via a lead line for data.
An LSI device on which a first chip and a second chip to be connected by lead lines are mounted,
- said first chip comprising a first data input/output terminal to be supplied with a data signal, and a first input/output circuit, connected to said first data input/output terminal, for outputting a data signal in said first chip to said first data input/output terminal in response to a first output clock in said first chip, and inputting said data signal supplied to said first data input/output terminal and transferring said data signal inside in response to a first transfer clock in said first chip,
- said second chip comprising a second data input/output terminal to be supplied with a data signal, and a second input/output circuit, connected to said second data input/output terminal, for outputting a data signal in said second chip to said second data input/output terminal in response to a second output clock in said second chip, and inputting said data signal supplied to said second data input/output terminal and transferring said data signal inside in response to a second transfer clock in said second chip,
- said first output clock and said first transfer clock being generated from a reference clock in said first chip, said reference clock being transferred via said lead lines to said second chip to thereby generate said second output clock and said second transfer clock,
- said first data input/output terminal in said first chip and said second data input/output terminal in said second chip being arranged on opposing sides of both chips and being connected together via a data lead line.
Dependencies are inferred from the claim text.