Address generating circuit of semiconductor memory device
AssigneeSumsung Electronics Co., Ltd.
InventorYoung-Dae Lee
Life of this patent
Estimating the term…
Abstract
An address generating circuit of a semiconductor memory device includes address buffers, multiplexers, shift registers and latches by which high-bit and low-bit write/read addresses in a normal mode and in a burst mode are routed through separate paths. A control circuit routes the high-bit read address data through a different path than the high bit write address data. The paths are joined to a common output latch, and include differential delays for the data. Similarly, the low-bit read continuing burst address data is routed through a different path than the low bit continuing burst write address data.
Claims30
An address generating circuit of a semiconductor memory device comprising:
- a first multiplexer for generating high level bits in response to an external address that is one of a read address and a write address;
- a read address high data path and a write address high data path for transferring bits generated by the first multiplexer, the high data paths distinct from each other at least in part;
- a first differential delay for delaying bits transferred through the read address high data path differentially from bits transferred through the write address high data path;
- and
- a control circuit for routing the generated high level bits that correspond to a read address through the read address high data path, and for routing the generated high level bits that correspond to a write address through the write address high data path.
An address generating circuit of a semiconductor memory device comprising:
- a high bit read address generating means for generating a read address of a bit of high level;
- a high bit write address generating means for generating a write address of a high bit delayed by a first predetermined cycle;
- a low bit read address generating means for generating a read address in normal and burst modes of a low bit;
- a low bit write address generating means for generating a write address in normal and burst modes of low bit delayed by a second predetermined cycle;
- and
- a control means for controlling the high bit read address generating means, the high bit write address generating means, the low bit read address generating means, and the high bit write address generating means.
An address generating circuit of a semiconductor memory device comprising:
- a high bit read address generating means for generating a read address of a high bit delayed by a first predetermined cycle;
- a high bit write address generating means for generating a write address of a high bit;
- a low bit read address generating means for generating a read address in normal and burst modes of a low bit delayed by a second predetermined cycle;
- a low bit write address generating means for generating a write address in normal and burst modes of low bit;
- and
- a control means for controlling the high bit read address generating means, the high bit write address generating means, the low bit read address generating means, and the high bit write address generating means.
An address generating circuit of a semiconductor memory device comprising:
- a high bit read address generating means for generating a read address of a high-level bit delayed by a first predetermined cycle;
- a high bit write address generating means for generating a write address of a high bit delayed by a second predetermined cycle;
- a low bit read address generating means for generating normal/burst read addresses of low bit delayed by a third predetermined cycle;
- a low bit write address generating means for generating normal/burst write addresses of low bit delayed by a fourth predetermined cycle;
- and
- a control means for controlling the high bit read address generating means, the high bit write address generating means, the low bit read address generating means, and the high bit write address generating means.
Dependencies are inferred from the claim text.