Semiconductor memory device capable of reducing the effect of crosstalk noise between main bit lines and virtual main grounding lines

Abstract

This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit lines in the OPEN state, based on an address signal; a plurality of virtual main grounding lines; and a virtual main grounding line controller for controlling whether to impress a specific voltage on the virtual main grounding lines, impress a grounding voltage on the virtual main grounding lines, or place the virtual main grounding lines in the OPEN state, based on an address signal. The main bit line controller and the virtual main grounding line controller control the voltage impression states of the main bit lines and the virtual main grounding lines respectively, so that, when accessing a memory cell, the relative positional relationship of the voltage level states of the virtual main grounding lines and other main bit lines that are adjacent to and at specific intervals of space from the main bit line connecting the selected memory cell and the sense amplifier, will be the same for any memory cell selected.

Dependencies are inferred from the claim text.