Semiconductor memory device including sense amplifier circuit differing in drivability between data write mode and data read mode

A semiconductor memory device comprising:

• a plurality of memory cells arranged alignedly in at least one column;
• a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;
• a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair;
• and
• sense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state,
• wherein said sense amplifier activation control circuitry comprises:
• a first sense power supply line for transmitting a first sense power supply voltage,
• a second sense power supply line for transmitting a second sense power supply voltage,
• a first sense driver transistor connected between said first sense power supply line and a first source node of said sense amplifier, and having a gate coupled to a first sense drive line transmitting a first sense amplifier drive signal,
• a second sense drive transistor connected between said second sense power supply line and a second source node of said sense amplifier, and having a gate coupled to a second sense drive line transmitting a second sense amplifier drive signal, and
• a switch circuit responsive to activation of said write operation activation signal for short-circuiting the first and second sense amplifier drive lines.

A semiconductor memory device comprising:

• a plurality of memory cells arranged alignedly in at least one column;
• a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;
• a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair;
• and
• sense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state,
• wherein said bit line pair comprises
• a first bit line pair to which a plurality of memory cells are connected,
• a second bit line pair to which a plurality of memory cells are connected, and
• a common bit line pair to which said sense amplifier is connected, wherein
• said semiconductor memory device further comprises:
• a first bit line isolation control gate connected between said first bit line pair and said common bit line pair for connecting said first bit line pair with said common bit line pair according to a first bit line isolation control signal, and
• a second bit line isolation control gate connected between said second bit line pair and said common bit line pair for connecting said second bit line pair with said common bit line pair according to a second bit line isolation control signal,
• wherein said sense amplifier activation control circuitry comprises
• a first sense power supply line for transmitting a first sense power supply voltage to said sense amplifier,
• a second sense power supply line for transmitting a second sense power supply voltage to said sense amplifier,
• a first sense amplifier drive transistor connected between said sense power supply line and a first source node of said sense amplifier, rendered to connect said first sense power supply line with the first source node of said sense amplifier,
• a second sense amplifier drive transistor connected between said second sense power supply line and a second source node of said sense amplifier, rendered conductive, in response to activation of a second sense amplifier drive signal, to connect said second sense power supply line with the second source node of said sense amplifier,
• a control circuit responsive to activation of said sense amplifier activation signal for activating a main sense amplifier drive signal,
• a first tristate buffer circuit responsive to a first block specify signal for generating said second bit line isolation control signal,
• a second tristate buffer circuit responsive to a second block specify signal for generating said first bit line isolation control signal,
• a third buffer circuit responsive to said main sense amplifier drive signal for generating the first and second sense amplifier drive signals,
• a pulse generation circuit generating a pulse signal entering an active state for a predetermined time in response to activation of said main sense amplifier drive signal for setting the first to third buffer circuits at an output high impedance state when the pulse signal is active,
• a first switch circuit responsive to activation of the pulse signal from said pulse generation circuit for equalizing the first and second sense amplifier drive signals,
• a second switch circuit for equalizing said first bit line isolation control signal and said first sense amplifier drive signal according to said first block specify signal and said pulse signal, and
• a third switch circuit for equalizing said second sense amplifier drive signal and said second bit line isolation control signal according to activation of said pulse signal and said second bit line isolation control signal, and
• wherein said second bit line isolation control signal enters an inactive state and said first bit line isolation control gate is rendered nonconductive when said first block specify signal is active, and said first bit line isolation control signal enters an inactive state and said first bit line isolation control gate is rendered nonconductive when said second block specify signal is active.

A semiconductor memory device comprising:

• a plurality of memory cells arranged alignedly in at least one column;
• a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;
• a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair;
• sense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state;
• and
• a cancel circuit for canceling reduction in drivability of the sense amplifier by said sense amplifier activation control circuitry when a write data mask designating signal that inhibits data writing to a selected memory cell of said plurality of memory cells is active.

A semiconductor memory device comprising:

• a plurality of memory cells arranged alignedly in at least one column;
• a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;
• a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair;
• sense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state;
• a read out data transmission line for transmitting data read out from a selected memory cell of said plurality of memory cells;
• a write data line provided separate from said read out data line, for transmitting write data to said selected memory cell;
• and
• a write driver for transmitting a write data signal corresponding to externally applied write data to said write data line according to write data when activated,
• said write driver including a precharge circuit for precharging said write data line to a voltage level identical to a precharge voltage of each bit line of said bit line pair when said write operation activation signal is inactivated,
• wherein said at least one column includes a plurality of columns, and
• wherein said write driver further comprises a drive circuit transmitting said write data signal according to the write data when active,
• said drive circuit rendered active in response to activation of said write operation activation signal and inactivation of a mask designating signal masking the write data, and entering an output high impedance state when inactive, and
• said precharge circuit rendered inactive upon activation of a column select signal driving a write column select gate for connecting a selected column to said write data line when said mask designating signal is inactive.

A semiconductor memory device comprising:

• a plurality of memory cells arranged alignedly in at least one column;
• a bit line pair arranged corresponding to the memory cells arranged in said at least one column, and having said plurality of memory cells connected thereto;
• a sense amplifier coupled to said bit line pair for sensing, amplifying and latching a voltage difference of said bit line pair;
• sense amplifier activation control circuitry coupled to said sense amplifier for activating said sense amplifier according to a sense amplifier activation signal, said sense amplifier activation control circuitry being responsive to a write operation activation signal designating data writing of external data to a selected memory cell for reducing current drivability of said sense amplifier in an active state;
• a read out data transmission line for transmitting data read out from a selected memory cell of said plurality of memory cells;
• a write data line provided separate from said read out data line, for transmitting write data to said select memory cell;
• and
• a write driver for transmitting a write data signal corresponding to externally applied write data to said write data line according to write data when activated, said write driver including a precharge circuit for precharging said write data line to a voltage level identical to a precharge voltage of each bit line of said bit line pair when said write operation activations signal is inactive,
• wherein said precharge circuit also precharges said write data line to the precharge voltage of the bit lines when said mask designating signal is active to inhibit data writing into said selected memory cell.