Semiconductor memory device with fast input/output line precharge scheme and method of precharging input/output lines thereof

A semiconductor memory device comprising:

• a memory cell array comprising a first group of memory cells and a second group of memory cells;
• a first group of input-output (IO) line pairs at one side of the memory cell array, the first group of IO line pairs transferring data to and from the first group of memory cells;
• a second group of IO line pairs at the other side of the memory cell array, the second group of IO line pairs transferring data to and from the second group of memory cells;
• a clock buffer receiving an externally applied clock signal and producing a first clock signal and a second clock signal, the second clock signal leading the first clock signal;
• an address buffer having at least one latch, the latch holding an internally generated address in synchronization with a falling edge of the first clock signal so as to select one of the first and second groups of IO line pairs, the address buffer outputting a signal held therein in synchronization with an edge of the first clock signal;
• a full page mode detector that detects whether the device operates in a full page mode and activates a full page mode detection signal when the device operates in the full page mode;
• an address transition detector responsive to the full page mode detection signal, the address transition detector generating a first address transition detection signal when a first signal from an output terminal of the latch changes from a first level to a second level and generating a second address transition detection signal when a second signal from an input terminal of the latch changes from the first level to the second level, the first and second signals being complementary to each other;
• a precharge signal generator generating a first precharge signal or a second precharge signal in response to the address transition detection signal in the full page mode;
• and
• an IO line precharge circuit precharging, in response to the precharge signal, one of the first and second groups of IO line pairs in the full page mode.