US 6,205,068 B1 · Dynamic random access memory device having a divided precharge control scheme

Abstract

A random access memory device provides high speed access by utilizing a divided precharge control scheme to reduce the loading on equalization signal lines. The equalization lines are driven at voltages which are greater than the internal operating voltage of the device, thereby reducing the row precharge time and further increasing the access speed. The device includes a plurality of bit line pairs for transferring data from memory cells. Each bit line pair is coupled to a bit line equalization circuit which includes a pair of precharge transistors that precharge the bit lines in response to a first bit line equalization signal, and an equalization transistor that equalizes the voltage of the bit lines in response to a second bit line equalization signal. The first bit line equalization signal is preferably driven at a boost voltage level, and the second bit line equalization signal is preferably driven at an external voltage level. The memory device also includes a plurality of sense amplifiers, each of which has a pair of sense amplifier nodes that are precharged by a corresponding sense amplifier equalization circuit. Each sense amplifier equalization circuit includes a pair of precharge transistors that precharge the sense amplifier nodes to the precharge voltage in response to a first latch enable equalization signal, and an equalization transistor that equalizes the voltage of the sense amplifier nodes in response to a second latch enable equalization signal. A latch enable equalization signal generator similar to the bit line equalization signal generator generates the first and second latch enable equalization signals at the boost voltage level and the external voltage level, respectively, in response to the control signal.

Claims18

Dependent claims

A semiconductor memory device comprising:

an array having a plurality of memory cells;
a pair of bit lines coupled to the array;
a bit line equalization circuit coupled to the bit lines for precharging the bit lines with a precharge voltage prior to a read/write operation, wherein the bit line equalization circuit is activated by first and second bit line equalization signals having voltage levels that are substantially greater than an operating voltage of the device;
and
a bit line equalization signal generator coupled to the bit line equalization circuit for generating the first and second bit line equalization signals;
wherein the first bit line equalization signal has a high level equal to a boost voltage which is greater than an external power supply voltage.

3 more elements

An integrated circuit memory device comprising:

an array having a plurality of memory cells;
a pair of bit lines coupled to the array;
a sense amplifier coupled to the bit lines for amplifying a difference between voltages on the bit lines, wherein the sense amplifier includes first and second sense amplifier nodes;
a sense amplifier equalization circuit coupled to the sense amplifier for precharging the sense amplifier nodes with a precharge voltage prior to a read/write operation, wherein the sense amplifier equalization circuit is activated by first and second latch enable equalization signals having voltage levels that are substantially greater than an operating voltage of the device;
and
a latch enable equalization signal generator coupled to the sense amplifier equalization circuit for generating the first and second latch enable equalization signals.

3 more elements

A dynamic random access memory comprising:

a plurality of word lines arranged in a row direction;
a plurality of bit lines forming a plurality of pairs of bit lines which are arranged in a column direction;
a plurality of memory cells connected between each of the plurality of bit line pairs via a plurality of access transistors, the access transistors being controlled by different ones of the word lines;
a plurality of bit line equalization circuits coupled to corresponding bit line pairs, wherein each of the bit line equalization circuits precharges a corresponding pair of bit lines with a precharge voltage before a read or write operation is performed, wherein the bit line equalization circuits are activated by both a first bit line equalization signal having a voltage level equal to a boost voltage and a second bit line equalization signal having a voltage level equal to an external power supply voltage;
a bit line equalization signal generator coupled to the bit line equalization circuits for generating the first and second bit line equalization signals;
a plurality of sense amplifiers coupled to corresponding ones of the bit line pairs, wherein each sense amplifiers has a pair of sense amplifier nodes;
a plurality of sense amplifier equalization circuits coupled to corresponding ones of the sense amplifiers, wherein each of the sense amplifier equalization circuits precharges the sense amplifier nodes of a corresponding sense amplifier before a read or write operation is performed, and wherein the sense amplifier equalization circuits are activated by both a first latch enable equalization signal having a voltage equal the boost voltage and a second latch enable equalization signal having a voltage equal to the external power supply voltage;
and
a latch enable equalization signal generator coupled to the sense amplifier equalization circuits for generating the first and second latch enable equalization signals.

6 more elements

Dependencies are inferred from the claim text.

Dynamic random access memory device having a divided precharge control scheme

Life of this patent

Dynamic random access memory device having a divided precharge control scheme

Life of this patent

Abstract

Claims18