Semiconductor memory device having redundancy memory circuit

A semiconductor memory system comprising:

• a basic memory portion;
• a memory cell array for relief which stores plural pieces of information for identifying bit cells to be replaced and provides memory cells for replacing in bits arbitrary memory cells existing in said basic memory portion according to these pieces of information;
• a nonvolatile memory for supplying said information for identifying bit cells to be replaced to said memory cell array for relief;
• a decoder for allocating address signals be supplied to the basic memory portion to an index portion and a tag portion and for decoding an address allocated to the index portion;
• a comparator for comparing an address allocated to the tag portion with information specified by an output of the decoder out of information for identifying bit cells to be replaced, said information for identifying bit cells to be replaced being stored in the memory cell array for relief;
• and
• a selector for selecting and connecting either of memory cells in the basic memory portion and memory cells in the memory cell array for relief with the outside on the basis of an output of the comparator.