Semiconductor memory device having program circuit

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in the form of a matrix and a spare memory cell for repairing a faulty memory cell;
• a plurality of address program circuits, each of said plurality of address program circuits including an electric fuse and being capable of programming a repair address for repairing said faulty memory cell by blowing said electric fuse with a program voltage, wherein
• each of said plurality of memory cells includes:
• a memory cell transistor having a pair of source/drain regions formed in a first impurity region and a gate electrode formed on a channel region between said pair of source/drain regions with an insulator film therebetween, and
• a memory cell capacitor electrically connected with one of said pair of source/drain regions, and
• said electric fuse includes:
• a pair of third impurity regions formed in a second impurity region, having the same conductivity type as said second impurity region and corresponding to said pair of source/drain regions of said memory cell transistor, and
• a programming element, electrically connected to one of said pair of third impurity regions, corresponding to said memory cell capacitor.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells arranged in the form of a matrix and a plurality of spare memory cell columns each for repairing a faulty memory cell column including a faulty memory cell;
• a plurality of pairs of data lines for transferring data of said memory cell array;
• a plurality of pairs of spare data lines for transferring data of said plurality of spare memory cell columns;
• a data bus for transferring data between an external device and said memory cell array;
• a plurality of address program circuits, each of said address program circuits being capable of programming a repair column address for repairing said faulty memory cell column with a program voltage;
• a switching circuit switching electrical connection between each of said plurality of pairs of data lines and said data bus so that a pair of data lines for transferring data of said faulty memory cell column are disconnected from said data bus;
• and
• a selection circuit selectively connecting each of said plurality of pairs of spare data lines to said data bus in response to connection between said plurality of pairs of data lines and said data bus.