Apparatus and method for efficiently correcting defects in memory circuits
AssigneeInternational Business Machines Corporation
InventorsAnthony Gus Aipperspach, Sheldon Bernard Levenstein
Life of this patent
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Abstract
Defects in memory circuit (100) are efficiently corrected by selectively blowing fuses in a first plurality of fuses to describe a cell location of a defective cell within any of several memory array portions (110). Fuses in a second plurality of fuses are blown to describe indicate the particular memory array portion (112) containing the defective memory cell. During operation of the memory circuit (100), the cell location is forwarded to the memory array portion (112) containing the defective memory cell and a redundant memory cell (206) is used for data storage at the memory array portion (112) having a defective memory cell.
Claims24
A fuse circuit for indicating a defective memory cell within a memory array, the fuse circuit comprising:
- a first plurality of fuses selectively opened to describe a first cell location within any of a plurality of memory array portions of the memory array;
- and
- a second plurality of fuses associated with the first plurality of fuses and selectively opened to indicate a first defective memory portion of the plurality of memory array portions.
A memory circuit comprising:
- a memory array having a plurality of memory cells arranged in a plurality of memory array portions of the memory array;
- a fuse circuit adapted to describe a cell location within any one of the plurality of memory array portions and adapted to indicate a defective memory array portion;
- and
- a fuse controller adapted to forward the cell location described by the fuse circuit to the defective memory portion based on information indicated by the fuse circuit.
A memory circuit comprising:
- a memory array having a plurality of memory cells arranged in a plurality of memory array portions of a memory array;
- a fuse circuit having a first plurality of fuses selectively opened to describe a first cell location within any of the plurality of memory array portions and having a second plurality of fuses associated with the first plurality of fuses and selectively opened to indicate a defective memory portion of the plurality of memory array portions;
- and
- a fuse controller adapted to forwarding the first cell location described by the first plurality of fuses to the defective memory portion based on information indicated by the second plurality of fuses.
A method comprising the steps of:
- selectively opening any of a first plurality of fuses to describe a cell location within any of a plurality of memory array portions of a memory array;
- selectively opening any of a second plurality of fuses to indicate a defective memory array portion of the memory array.
A method comprising the steps of:
- determining a defective memory array portion of a plurality of memory array portions of a memory array;
- determining a cell location of a defective memory cell within the defective memory array portion;
- selectively opening any of a first plurality of fuses to describe the cell location within any of a plurality of memory array portions of the memory array;
- selectively opening any of a second plurality of fuses to indicate the defective memory array portion of the memory array.
Dependencies are inferred from the claim text.