CAS latency control circuit
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsDong Kyeun Kim, Sung Hoon Kim
Life of this patent
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Abstract
A Column Address Strobe (CAS) latency control circuit for a SDRAM and a layout of the same allows an adequate CAS latency operation allowance at a high operation frequency. The SDRAM includes a plurality of banks each having ‘n’ main amplification units, ‘n’ bit data buses disposed between the plurality of banks each shared by respective main amplification units, ‘n’ CAS latency control circuits disposed concentrated central to the data buses one to one matched to the data buses, ‘n’ DQ blocks disposed connected to outputs of respective CAS latency control circuits in lengths different from one another, and a clock buffer for applying a clock signal to the CAS latency control circuits.
Claims20
A latency control circuit comprising:
- a control circuit adapted to receive a clock signal to regulate data output and a plurality of input signals to provide first, second and third control signals;
- a first logic gate to logically combine a CAS latency control signal with data;
- a first latch to pass or latch data from said first logic gate in response to the third control signal from said control circuit unit;
- a second logic gate to logically combine a second logic gate control signal with data;
- a second latch to pass or latch data from said first latch or to pass or latch a data from said second logic gate in response to the second control signal from the control circuit unit;
- and
- a third latch to pass data from said second latch to a data output buffer or latch the data in response to the first control signal from said control circuit unit.
A latency control circuit, comprising:
- a first data latch responsive to a first control signal;
- a controller, wherein said controller receives a clock signal and generates the first control signal, said first data latch being coupled to receive first and second input signals and output a first output signal, wherein the first output signal is one of (1) the first input signal forwarded without latching through said first data latch, (2) the first input signal latched and subsequently forwarded through said first data latch, (3) the second input signal forwarded without latching through said first data latch, and (4) the second input signal latched and subsequently forwarded through said first data latch, in response to the first control signal.
Dependencies are inferred from the claim text.