Efficient back bias (VBB) detection and control scheme for low voltage drams
AssigneeTexas Instruments Incorporated
InventorsVipul Surlekar, Sadashiva Rao
Life of this patent
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Abstract
An efficient back bias (VBB) detection and control circuit make possible a low voltage memory device and includes an on-chip VBB level sensor (38) that includes a dynamic voltage reference shift circuit (40, 42, 44, 46) for establishing a first voltage level (−(|2VTP|+VTN)) during power-up and a second voltage level (−|2VTP| during normal operation. The first voltage level is of a deeper level for achieving a short power-up interval. The second voltage level has a level less deep than said first voltage for achieving low power operation.
Claims29
A voltage detection circuit to sense the level of an on-chip generated voltage comprising:
- a first diode-connected transistor having its current path connected between a voltage terminal having the generated voltage thereon and a first node;
- a second transistor having its current path connected between the first node and an output node, and wherein the gate of the second transistor is connected to a control signal, the control signal being at an inactive voltage level during a first time frame of operation thereby enabling the second transistor during the first time frame of operation only if the generated voltage reaches a particular threshold level, and the control signal being at an active voltage level during a second time frame of operation, separate from the first time frame of operation, thereby enabling the second transistor for the second time frame of operation.
A voltage detection circuit to detect the level of an on-chip generated voltage comprising:
- a first diode-connected transistor and a second transistor having their current paths connected in series between a voltage terminal having the generated voltage thereon and a first node;
- and
- wherein the gate of the second transistor is connected to a control signal, the control signal being at an inactive voltage level during a first time frame of operation thereby enabling the second transistor during the first time frame of operation only if the generated voltage reaches a particular threshold level and thus including the second transistor in the sensing of the generated voltage, and the control signal being at an active voltage level during a second time frame of operation, separate from the first time frame of operation, thereby enabling the second transistor during the second time frame of operation and bypassing the second transistor in the sensing of the generated voltage.
A voltage detection circuit to detect a first level of an on-chip generated voltage during a first time frame of operation and to detect a second level of the on-chip generated voltage during a second time frame of operation, comprising:
- a first diode-connected transistor and a second transistor having their current paths connected in series between a voltage terminal having the generated voltage thereon and a first node, the gate of the second transistor being connected to a control signal;
- and
- wherein the control signal is at an inactive voltage level during the first time frame of operation thereby enabling the second transistor during the first time frame of operation only if the generated voltage reaches the first level and thus including the threshold voltage (Vt2) of the second transistor in determining the first level of the generated voltage to be sensed during the first time frame of operation;
- and
- wherein the control signal is at an active voltage level during the second time frame of operation, the second time frame of operation being separate from the first time frame of operation, thereby enabling the second transistor during the second time frame of operation and thus not including the threshold voltage (Vt2) of the second transistor in determining the second level of the generated voltage being sensed during the second time frame of operation.
Dependencies are inferred from the claim text.