Semiconductor memory device having improved cell array layout
AssigneeKabushiki Kaisha Toshiba
InventorsMasao Kuriyama, Shigeru Atsumi
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Abstract
Each of first and second cell array groups has a cell array and a row decoder. Circuit blocks including a reset transistor, a Y selector, a write transistor, a block decoder, and a source decoder except the cell array and row decoder are arranged in the area between the first and second cell array groups. Since an address signal, a control signal, and a power supply common to the circuit blocks can be shared, the layout area can be reduced.
Claims13
A semiconductor memory device having a core portion including a cell array, comprising:
- a first cell array group arranged in said core portion and including a plurality of cell arrays and a row decoder;
- a second cell array group arranged substantially parallel to said first cell array group and including a plurality of cell arrays and a row decoder;
- and
- circuit blocks laid out in an area between said first and second cell array groups, wherein said circuit blocks include a reset transistor for resetting bit lines of said cell array, a Y-selector for selecting said bit lines, and a write transistor for applying a high voltage to said bit lines of memory cells in a write operation, and wherein said reset transistor, said Y selector, and said write transistor are respectively laid out from a side adjacent to said cell array.
A semiconductor memory device based on a double word line scheme, comprising:
- a first cell array group including a plurality of cell arrays, a row local decoder for selecting word lines of said cell arrays, and a row global decoder for selecting said row local decoder;
- a second cell array group including a plurality of cell arrays, a row local decoder for selecting word lines of said cell arrays, and a row global decoder for selecting said row local decoder;
- and
- circuit blocks laid out in an area between said first and second cell array groups and including a row partial decoder for outputting a selection signal to be supplied to said row local decoder.
A semiconductor memory device comprising:
- a first cell array having large regular blocks;
- a second cell array having irregular blocks each smaller than said regular block;
- a Y selector constituted by a block selector for selecting blocks of said first and second cell arrays and a column selector for selecting columns in said blocks;
- data lines extending along said regular blocks and adapted to connect columns selected by said Y selector to a sense amplifier;
- and
- subdata lines arranged on extended lines of said data lines along said irregular blocks, connected to said selected columns through said column selector, and connected to said data lines through said block selector;
- wherein said regular blocks are laid out near said sense amplifier, and said irregular blocks are arranged in a distant area from said sense amplifier.
Dependencies are inferred from the claim text.