Decoder connection configuration for memory chips with long bit lines

A memory chip, comprising:

• a memory cell array having an edge and a bit line twist region;
• long bit lines running in said memory cell array in a first direction and forming bit-line twists in said bit line twist region;
• word lines crossing said long bit lines in said memory cell array and running in a second direction;
• a decoder region adjoining said edge of said memory cell array and running in said first direction, said decoder region having lateral edges and a zone adjoining said bit line twist region;
• word line decoders lying in said decoder region in a first metallization plane;
• supply lines for said word line decoders, routed in said decoder region in a second metallization plane lying above said first metallization plane;
• and
• a layer disposed between said first metallization plane and said second metallization plane and having plated-through holes formed therein running between said first metallization plane and said second metallization plane at said lateral edges of said decoder region, and additional plated-through holes formed in said layer running between said first metallization plane and said second metallization plane in said zone of said decoder region adjoining said bit line twist region.