Apparatus and method having improved memory controller request handler

For operating a system comprising an input device for receiving inputs from a user of the system;

• a central processing unit (CPU) interfacing with the input device and responding to the inputs by performing a processing function producing an output including display data;
• a memory device interfacing with the CPU to provide memory storage of commands and data used by the CPU;
• a plurality of output devices, each of which receives the output from the CPU and provides a sensible output response and includes a display device providing a visible image to the user in response to the display data;
• a dynamic random access memory (DRAM);
• and a video display controller (VDC) interfacing the DRAM to the CPU to forward display data thereto for temporary storage, a method comprising the steps of:
• A) including in the VDC a plurality of display first-in-first-out (FIFO) memories, each display FIFO:
• i) being associated with a different one of the display devices;
• ii) interfacing with the DRAM for receiving and temporarily holding display data to be imminently presented on the display device;
• iii) being of certain capacity and continuously providing the data to its associated display device while receiving data from the DRAM only intermittently;
• and
• iv) issuing a low-priority (FIFOLO) or high-priority (FIFOHI) request for access to the DRAM dependent respectively on whether a data level in the display FIFO is below a FIFOLO pointer or is below a FIFOHI pointer;
• and
• B) including in the VDC a sequencer and controller unit (SEQC);
• and
• C) using the SEQC to arbitrate access to the DRAM among the display FIFOs according to a multi-tiered priority in which the FIFOs' low-priority requests are ranked within a lower tier and the FIFOs' high-priority requests are ranked within a tier above the lower tier in an order opposite the order in which those FIFOs' low-priority requests are ranked in the lower tier, lower-tier requests not being enabled to interrupt any existing DRAM access, and requests in a tier above the lower tier being enabled to interrupt an existing DRAM access granted by the SEQC in response to a lower-tier request.

A video display controller (VDC) that interfaces a dynamic access memory (DRAM) to a central processing unit (CPU) that provides display data to a plurality of display devices, the VDC comprising:

• i) a plurality of display first-in-first-out (FIFO) memories, each display FIFO:
• a) being associated with a different one of the display devices;
• b) interfacing with the DRAM for receiving and temporarily holding display data to be imminently presented on the display device;
• c) being of certain capacity and continuously providing the data to its associated display device while receiving data from the DRAM only intermittently;
• and
• d) issuing a low-priority (FIFOLO) or high-priority (FIFOHI) request for access to the DRAM dependent respectively on whether a data level in the display FIFO is below a FIFOLO pointer or is below a FIFOHI pointer;
• and
• ii) a sequencer and controller unit (SEQC) arbitrating access to the DRAM among the display FIFOs according to a multi-tiered priority in which the FIFOs' low-priority requests are ranked within a lower tier and the FIFOs' high-priority requests are ranked within a tier above the lower tier in an order opposite the order in which those FIFOs' low-priority requests are ranked in the lower tier, lower-tier requests not being enabled to interrupt any existing DRAM access, and requests in a tier above the lower tier being enabled to interrupt an existing DRAM access granted by the SEQC in response to a lower-tier request.