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US 6,204,863 B1Granted
Method for dynamic XY tiled texture caching
AssigneeCirrus Logic, Inc.
InventorDaniel P. Wilde
Life of this patent
Estimating the term…
Abstract
A method for dynamically caching display list information to an internal on-chip cache performs UV title read hit comparisons to determine whether to read display list parameters from internal cache or external memory.
Claims18
A method for dynamically caching a texture map as a tile of texels into an internal memory system of a graphics processor, comprising the steps of:
- designating bit values of a new UV texel address to represent a number of texels for a tile and other bit values of the new UV texel address to represent an UV tile address of the tile;
- receiving, by a graphics processor having at least a polygon engine, a texture engine with at least a texture cache controller and tag registers, and the internal memory system, a request for the new UV texel address of a new texture map;
- determining the UV tile address from the new UV texel address by truncating, by the texture cache controller, the bit values that represent the number of texels for the tile from the new UV texel address so that the other bit values that represent the UV tile address remain;
- comparing, by the texture engine, the UV tile address with UV tile addresses latched into the tag registers from previous UV texel address requests;
- and
- in response to the UV tile address not being among latched UV tile addresses of previous UV texel address requests, latching, by the texture engine, the UV tile address into one of the tag registers and retrieving and caching, by the texture engine, the tile at the UV tile address from an external memory system into the internal memory system.
3 more elements
A graphics system for rendering texture map information representative of graphics primitives on a computer display, comprising:
- a host processor for generating display list information of parameter values defining primitives;
- an external system memory coupled to said host processor for storing the display list information;
- and
- a graphics processor coupled to the host processor and the system memory for processing the texture map information;
- wherein the graphics processor has at least a polygon engine, a texture engine with at least a texture cache controller and tag registers, and an internal memory system;
- wherein bit values of a new UV texel address are designated to represent a number of texels for a tile and other bit values of the new UV texel address are designated to represent an UV tile address of the tile;
- wherein the graphics processor receives a request for the new UV texel address of a new texture map;
- wherein the UV tile address is determined from the new UV texel address by the texture cache controller truncating the bit values that represent the number of texels for the tile from the new UV texel address so that the other bit values that represent the UV tile address remain;
- wherein the texture engine compares the UV tile address with UV tile addresses latched into the tag registers from previous UV texel address requests;
- and
- wherein, in response to the UV tile address not being among latched UV tile addresses of previous UV texel address requests, the texture engine latches the UV tile address into one of the tag registers and the texture engine retrieves and caches the tile at the UV tile address from the external memory system into the internal memory system.
8 more elements
In a computer system having a graphics processor for processing graphics information, said graphics processor comprising:
- at least a polygon engine, a texture engine with at least a texture cache controller and tag registers, and an internal memory system coupled to each other;
- and
- wherein bit values of a new UV texel address are designated to represent a number of texels for a tile and other bit values of the new UV texel address are designated to represent an UV tile address of the tile;
- wherein the graphics processor receives a request for the new UV texel address of a new texture map;
- wherein the UV tile address is determined from the new UV texel address by the texture cache controller truncating the bit values that represent the number of texels for the tile from the new UV texel address so that the other bit values that represent the UV tile address remain;
- wherein the texture engine compares the UV tile address with UV tile addresses latched into the tag registers from previous UV texel address requests;
- and
- wherein, in response to the UV tile address not being among latched UV tile addresses of previous UV texel address requests, the texture engine latches the UV tile address into one of the tag registers and the texture engine retrieves and caches the tile at the UV tile address from an external memory system into the internal memory system.
5 more elements
Dependencies are inferred from the claim text.