Circuits and methods for gain ranging in an analog modulator and systems using the same
AssigneeCirrus Logic, Inc.
InventorRex Baird
Life of this patent
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Abstract
Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.
Claims20
Analog modulator circuitry comprising:
- an integrator having first and second inputs;
- first switched-capacitor circuitry for selectively sampling a first amount of charge from a feedback signal to first and second feedback capacitors during a first timing phase and coupling said first amount of charge from said first and second feedback capacitors to said first and second inputs of said integrator stage during a second timing phase;
- second switched-capacitor circuitry for selectively sampling a second amount of charge from said feedback signal to third and fourth capacitors in parallel with said first and second capacitors during said first timing phase and coupling said second amount of charge from said third and fourth capacitors during said second timing phase to said first and second inputs of said integrator stage to selectively compensate for an offset of an input signal to said integrator stage with respect to a reference voltage;
- and
- switching circuitry for selectively cross-coupling said third and fourth capacitors with said inputs of said integrator.
An analog modulator comprising:
- an integrator including an integrator stage having inverting and non-inverting inputs;
- and
- feedback circuitry comprising:
- first switched-capacitor circuitry for sampling a feedback signal to charge first and second feedback sampling capacitors during a first timing phase and selectively coupling the charge on the first and second feedback sampling capacitors to the inputs of the integrator stage during a second timing phase;
- and
- second switched-capacitor circuitry activated as a function of a relationship between an input signal to the modulator and a reference signal for sampling the feedback signal to charge third and fourth feedback sampling capacitors during the first phase and selectively coupling the charge from the third and fourth capacitors to the inputs of the integrator stage during the second phase.
A method for centering an input signal having a predetermined relationship with a reference voltage in the dynamic range of an analog modulator comprising the steps of:
- selectively charging first and second capacitors by sampling a modulator feedback signal;
- coupling the charge on the first and second capacitors to the capacitors of an analog integrator stage;
- selectively charging third and fourth capacitors by sampling the modulator feedback signal, the third and fourth capacitors having capacitances less than the capacitances of the first and second capacitors;
- and
- selectively coupling the charge on the third and fourth capacitors to the integrator stage to selectively add or subtract charge from the charge contributed by the first and second capacitors.
A processing device having a delta-sigma modulator operable to center a received input signal approximately about a reference voltage comprising:
- at least one integrator including an analog integrator stage and feedback circuitry, said feedback circuitry comprising:
- circuitry for selectively sampling a first amount of charge from a feedback signal to first and second capacitors and for selectively coupling said first amount of charge from said first and second capacitors to first and second inputs of said integrator stage;
- and
- circuitry for selectively sampling a second amount of charge from said feedback signal to third and fourth capacitors and coupling said second amount of charge from said third and fourth to said first and second inputs of said integrator stage to selectively add and subtract said second amount of charge from said first amount of charge.
Dependencies are inferred from the claim text.