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US 6,204,784 B1Granted
Multiple analog to digital converter clock phase alignment technique using varactor diodes
AssigneeRaytheon Company
InventorRoy G. Hatfield
Life of this patent
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AssigneeRaytheon Company
InventorRoy G. Hatfield
Estimating the term…
An analog to digital converter system with clock timing compensation includes an analog to digital converter circuit having an input terminal for receiving an analog signal to be sampled and converted to a digital value, one or more output terminals providing one or more logical output signals, and a clock terminal for receiving a sampling clock signal for clocking the sampling of the input signal. A thermally compensated clock circuit is responsive to a clock signal for providing the sampling clock signal, and includes a low pass filter circuit comprising a resistor element and a varactor diode, and a varactor bias network for providing a thermally compensated varactor bias voltage to the varactor diode. The clock timing circuit with varactor diodes can be used to provide very fine resolution adjustments to the individual clock circuits in a multiple analog to digital converter circuit system. The thermally compensated varactor bias networks allow the clock timing to stay within specification over a wide temperature range.
An analog to digital converter system with clock timing compensation, comprising:
In a ping-pong analog-to-digital converter (ADC) circuit employing multiple ADC circuits, and wherein a first ADC circuit is clocked by a first phase of a sampling clock, and a second ADC circuit is clocked by the second phase of the sampling clock 180° out-of-phase with the first phase, a thermally compensated clock timing delay circuit comprising:
An analog-to-digital converter (ADC) system, comprising:
Dependencies are inferred from the claim text.