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AssigneeECI Telecom Ltd.
InventorsAnatoli Rapoport, Emanuel Nachum
Estimating the term…
Apparatus for clock signals distribution with continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU. Switching is transparent to load circuits which utilize these clock signals, by continuously keeping the output clock signals in the CDU and the redundant CDU frequency and phase coherent, by generating each output clock signal from a reference signal, using an adaptive PLL circuitry at each CDU, and pre-adjusting the phase of each output clock signal of the redundant CDU to the corresponding output clock signal of the CDU. In the event of a failure in the CDU, the output is taken from the redundant CDU immediately after failure detection. The phase of the reference frequency output clock signal of the standby CDU module is adjusted to the phase of the active CDU module by adding or subtracting an input signal to the phase error signal, which is generated in a PLL circuitry of the redundant CDU module. An adjustable delay line is used at each CDU to delay the clock signal that is provided from the active into the redundant CDU. The delay time is adjusted to obtain phase coherence between the high frequency outputs of the two CDUs and a fine adjustment on the reference frequency output clock signal. The redundant CDU module becomes active and connected to the load, whenever a failure is detected in the active CDU module.
A clock signal distribution apparatus for generating at least a first clock signal and at least a second redundant clock signal, said second clock signal being phase and frequency coherent to said first clock signal, said apparatus comprising a pair of first and second CDU modules, each CDU module being capable to operate in active or standby mode, in response to a corresponding control signal, an output clock signal of the active CDU module being locked to a reference input signal, an output clock signal of the standby CDU module being locked and phase coherent to the output clock signal of the active CDU module, said active mode characterized by frequency filtering response being different from the response in the standby mode.
A method for clock signals distribution having continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU, said switching capability being transparent to load circuits utilizing said clock signals, comprising continuously keeping corresponding output clock signals in said CDU and said redundant CDU, frequency and phase coherent, by generating each output clock signal from a reference signal using an adaptive PLL circuitry at each CDU, and preadjusting the phase of each output clock signal of said redundant CDU to the corresponding output clock signal of said CDU, said PLL circuitry having an active mode and a standby mode with different response characteristics;
A method for clock signals distribution having continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU, said switching capability being transparent to load circuits utilizing said clock signals, comprising continuously keeping corresponding output clock signals in said CDU and said redundant CDU, frequency and phase coherent, by generating each output clock signal from a reference signal using an adaptive PLL circuitry at each CDU, and preadjusting the phase of each output clock signal of said redundant CDU to the corresponding output clock signal of said CDU, said PLL circuitry having an active mode and a standby mode with different response characteristics;
A method for clock signals distribution having continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU, said switching capability being transparent to load circuits utilizing said clock signals, comprising continuously keeping corresponding output clock signals in said CDU and said redundant CDU, frequency and phase coherent, by generating each output clock signal from a reference signal using an adaptive PLL circuitry at each CDU, and preadjusting the phase of each output clock signal of said redundant CDU to the corresponding output clock signal of said CDU, said PLL circuitry having an active mode and a standby mode with different response characteristics;
A method for clock signals distribution having continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundant CDU, said switching capability being transparent to load circuits utilizing said clock signals, comprising continuously keeping corresponding output clock signals in said CDU and said redundant CDU, frequency and phase coherent, by generating each output clock signal from a reference signal using an adaptive PLL circuitry at each CDU, and preadjusting the phase of each output clock signal of said redundant CDU to the corresponding output clock signal of said CDU, said PLL circuitry having an active mode and a standby mode with different response characteristics;
A method for clock signal distribution having continuous switching capability between the outputs of a Clock Distribution Unit (CDU) and of a redundancy CDU, said switching capability being transparent to load circuits utilizing said clock signal, comprising;
Dependencies are inferred from the claim text.