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US 6,204,723 B1Granted
Bias circuit for series connected decoupling capacitors
AssigneeInternational Business Machines Corporation
InventorsRussell J. Houghton, Christopher P. Miller
Life of this patent
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Abstract
A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.
Claims8
A semiconductor circuit for providing decoupling capacitance for an internal semiconductor voltage supply comprising:
- a plurality of memory cell capacitors connected in series at a selected node;
- and
- a source of biasing voltage connected to the series connected memory cell capacitors at the selected node for maintaining the voltage level at the node lower than the voltage level of the internal semiconductor voltage supply wherein the source of biasing voltage provides a bias voltage Vbiasout and draws a quiescent current which is very low compared to the total current of the semiconductor chip and
- wherein the bias voltage VA has a voltage range between VAmin and VAmax, wherein the bias circuit provides an output bias current Ibiasout having a value near zero (0.0 mAmps) when VAmin is equal to or less than VAnom−½Vpeak, and when VAmax is equal to or greater than VAnom+½Vpeak.
1 more element
Dependencies are inferred from the claim text.